A multi-core processor includes a plurality of cores and a central dynamic voltage and frequency scaling (DVFS) system coupled to the plurality of core. The DVFS system is configured to receive power parameters and performance parameters for the plurality of cores. The power parameters may indicate power indices each respective core and the performance parameters may indicate performance for each respective core. The DVFS system may determine a power margin based on a target power budget for the multi-core processor and the power indices for the plurality of cores. For one or more cores of the plurality of cores, the DVFS system may dynamically allocate power to the core by determining an adjusted power index based on the power margin and the performance of the core. Accordingly, the DVFS system may dynamically balance performance and power of the cores.