Invention Publication
- Patent Title: ARCHITECTURE FOR COMPUTING SYSTEM PACKAGE
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Application No.: US18761884Application Date: 2024-07-02
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Publication No.: US20240355746A1Publication Date: 2024-10-24
- Inventor: Chen-Hua Yu , Chieh-Yen Chen , Chuei-Tang Wang , Chung-Hao Tsai
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Main IPC: H01L23/538
- IPC: H01L23/538 ; H01L21/48 ; H01L23/00 ; H01L23/48 ; H01L23/498 ; H01L25/10

Abstract:
A method includes forming a reconstructed wafer, which includes forming a redistribution structure over a carrier, bonding a first plurality of memory dies over the redistribution structure, bonding a plurality of bridge dies over the redistribution structure, and bonding a plurality of logic dies over the first plurality of memory dies and the plurality of bridge dies. Each of the plurality of bridge dies interconnects, and is overlapped by corner regions of, four of the plurality of logic dies. A second plurality of memory dies are bonded over the plurality of logic dies. The plurality of logic dies form a first array, and the second plurality of memory dies form a second array.
Information query
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