- 专利标题： TRANSISTOR ARRANGEMENT WITH A LOAD TRANSISTOR AND A SENSE TRANSISTOR
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申请号： US18760559申请日： 2024-07-01
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公开(公告)号： US20240355923A1公开(公告)日： 2024-10-24
- 发明人: Gerhard Noebauer
- 申请人： Infineon Technologies Austria AG
- 申请人地址： AT Villach
- 专利权人： Infineon Technologies Austria AG
- 当前专利权人： Infineon Technologies Austria AG
- 当前专利权人地址： AT Villach
- 优先权： EP 151843.2 2018.01.16
- 分案原申请号： US17104216 2020.11.25
- 主分类号： H01L29/78
- IPC分类号： H01L29/78 ; G01R19/00 ; H01L29/06 ; H01L29/08 ; H01L29/40
摘要：
A transistor arrangement includes a drift and drain region arranged in a semiconductor body and each connected to a drain node, a plurality of load transistor cells each comprising a source region integrated in a first region of the semiconductor body, a plurality of sense transistor cells each comprising a source region integrated in a second region of the semiconductor body, a first source node electrically connected to the source region of each of the plurality of the load transistor cells via a first source conductor, and a second source node electrically connected to the source region of each of the plurality of the sense transistor cells via a second source conductor, a resistance of the second source conductor is different from a resistance of the first source conductor, and the second source conductor comprises an elongated span with a plurality of meanders in which the connection line reverses its direction.
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