The present disclosure relates to an integrated chip including a bottom electrode arranged within a dielectric layer. A memory element is directly over the bottom electrode and is arranged within the dielectric layer. A top electrode is directly over the memory element and is arranged within the dielectric layer. A conductive via is directly over the top electrode. A pair of lines that extend along opposing sidewalls of the top electrode are directly over, and intersect, an uppermost surface of the memory element. The pair of lines are directly under, and intersect, a lowermost surface of the via.