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公开(公告)号：US20240365676A1
公开(公告)日：2024-10-31
申请号：US18770678
申请日：2024-07-12
发明人： YA-LING LEE , TSANN LIN , HAN-JONG CHIA
CPC分类号： H10N50/10 , G01R33/093 , G01R33/098 , G11C11/161 , H10B61/00 , H10N50/01 , H10N50/80 , H10N50/85
摘要： A magnetic tunnel junction (MTJ) element is provided. The MTJ element includes a hard bias layer, a reference layer disposed over the hard bias layer, a tunnel barrier layer disposed over the reference layer, a free layer disposed over the tunnel barrier layer, and a diffusion barrier layer disposed over the free layer wherein the diffusion barrier layer comprises an amorphous and nonmagnetic film of a form X-Z, where X is Fe or Co and Z is Hf, Y, or Zr. The MTJ element in accordance with the present disclosure exhibits a low resistance desired for a low-power write operation, and a high TMR coefficient desired for a low bit-error-rate (BER) read operation.
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公开(公告)号：US20240365564A1
公开(公告)日：2024-10-31
申请号：US18768995
申请日：2024-07-10
发明人： Chih-Fan Huang , Wen-Chiung Tu , Liang-Wei Wang , Dian-Hau Chen , Yen-Ming Chen
摘要： Semiconductor device and methods of forming the same are provided. A semiconductor device according to one embodiment includes a first source/drain feature and a second source/drain feature, a first metal line disposed in a first dielectric layer and electrically connected to the first source/drain feature, a second metal line disposed in the first dielectric layer and electrically connected to the second source/drain feature, and a first memory element disposed over the first dielectric layer and electrically connected to the first source/drain feature by way of the first metal line. A width of the first metal line is different from a width of the second metal line. By changing the widths of the first metal line and the second metal line, a source line series resistance of a semiconductor device can be advantageously reduced without changing a pitch of two metal lines.
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公开(公告)号：US20240363154A1
公开(公告)日：2024-10-31
申请号：US18763040
申请日：2024-07-03
发明人： Ming Yuan Song
CPC分类号： G11C11/1675 , G11C11/161 , G11C11/1659 , G11C11/1693 , H10B61/22 , H10N50/10 , H10N50/80
摘要： Some embodiments relate to a probabilistic random number generator. The probabilistic random number generator includes a memory cell comprising a magnetic tunnel junction (MTJ), and an access transistor coupled to the MTJ of the memory cell. A variable current source is coupled to the access transistor and is configured to provide a plurality of predetermined current pulse shapes, respectively, to the MTJ to generate a bit stream that includes a plurality of probabilistic random bits, respectively, from the MTJ. The predetermined current pulse shapes have different current amplitudes and/or pulse widths corresponding to different switching probabilities for the MTJ.
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4.发明授权公开(公告)号：US12133471B2
公开(公告)日：2024-10-29
申请号：US18238481
申请日：2023-08-26
发明人： Zihui Wang , Yiming Huai
IPC分类号： H10N50/10 , B82Y40/00 , G11C11/15 , G11C11/16 , H01F10/32 , H01F41/30 , H01L29/66 , H10B61/00 , H10N50/80 , H10N50/85
CPC分类号： H10N50/10 , G11C11/15 , G11C11/16 , G11C11/161 , H01F10/3286 , H01F10/329 , H01F41/302 , H01L29/66984 , H10B61/22 , H10N50/80 , H10N50/85 , B82Y40/00
摘要： A magnetic memory element including first and second magnetic free layers having a variable magnetization direction substantially perpendicular to layer planes thereof; a first perpendicular enhancement layer (PEL) interposed between the first and second magnetic free layers; first and second magnetic reference layers having a first invariable magnetization direction substantially perpendicular to layer planes thereof; a second PEL interposed between the first and second magnetic reference layers; an insulating tunnel junction layer formed between the first magnetic free layer and reference layer; an anti-ferromagnetic coupling layer formed adjacent to the second magnetic reference layer; a magnetic fixed layer formed adjacent to the anti-ferromagnetic coupling layer and having a second invariable magnetization direction substantially opposite to the first invariable magnetization direction; a non-magnetic layer comprising oxygen and a transition metal and formed adjacent to the second magnetic free layer; and a magnesium oxide layer formed adjacent to the non-magnetic layer.
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公开(公告)号：US12133470B2
公开(公告)日：2024-10-29
申请号：US18059073
申请日：2022-11-28
摘要： The present disclosure provides a semiconductor structure, including an Nth metal layer over a transistor region, where N is a natural number, and a bottom electrode over the Nth metal layer. The bottom electrode comprises a bottom portion having a first width, disposed in a bottom electrode via (BEVA), the first width being measured at a top surface of the BEVA, and an upper portion having a second width, disposed over the bottom portion. The semiconductor structure also includes a magnetic tunneling junction (MTJ) layer having a third width, disposed over the upper portion, a top electrode over the MTJ layer and an (N+1)th metal layer over the top electrode. The first width is greater than the third width.
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公开(公告)号：US20240357943A1
公开(公告)日：2024-10-24
申请号：US18760005
申请日：2024-06-30
发明人： Chiu-Jung Chiu , Ya-Sheng Feng , I-Ming Tseng , Yi-An Shih , Yu-Chun Chen , Yi-Hui Lee , Chung-Liang Chu , Hsiu-Hao Hu
摘要： A method for fabricating semiconductor device includes the steps of forming an inter-metal dielectric (IMD) layer on a substrate, forming a trench in the IMD layer, forming a synthetic antiferromagnetic (SAF) layer in the trench, forming a metal layer on the SAF layer, planarizing the metal layer and the SAF layer to form a metal interconnection, and forming a magnetic tunneling junction (MTJ) on the metal interconnection.
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公开(公告)号：US12127483B2
公开(公告)日：2024-10-22
申请号：US17388484
申请日：2021-07-29
发明人： Bi-Shen Lee , Hai-Dang Trinh , Hsun-Chung Kuang , Cheng-Yuan Tsai
摘要： Various embodiments of the present disclosure are directed towards an integrated circuit (IC) chip comprising a memory cell with a sidewall spacer, and/or an etch stop layer, doped to reduce charge accumulation at an interface between the sidewall spacer and the etch stop layer. The memory cell comprises a bottom electrode, a data storage element overlying the bottom electrode, and a top electrode overlying the data storage element. The sidewall spacer overlies the bottom electrode on a common sidewall formed by the data storage element and the top electrode, and the etch stop layer lines the sidewall spacer. The sidewall spacer and the etch stop layer directly contact at the interface and form an electric dipole at the interface. The doping to reduce charge accumulation reduces an electric field produced by the electric dipole, thereby reducing the effect of the electric field on the memory cell.
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公开(公告)号：US12119036B2
公开(公告)日：2024-10-15
申请号：US18096089
申请日：2023-01-12
CPC分类号： G11C11/1673 , G11C11/1675 , H10B61/00 , H10N50/80
摘要： A magnetic memory device may include a magnetic track, which is extended in a first direction, and a first electrode, which is provided at a biasing point of the magnetic track and is configured to apply a voltage to the magnetic track. The magnetic track includes a first region between a first end of the magnetic track and the biasing point and a second region between the biasing point and a second end of the magnetic track. The first electrode may be configured to cause a difference between a current density in the first region and a current density in the second region.
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公开(公告)号：US12114511B2
公开(公告)日：2024-10-08
申请号：US17462577
申请日：2021-08-31
发明人： Hui-Hsien Wei , Yen-Chung Ho , Chia-Jung Yu , Yong-Jie Wu , Pin-Cheng Hsu
摘要： A semiconductor device, an integrated circuit, and a method of manufacturing the same are provided. The semiconductor device includes a substrate, a thin-film transistor (TFT) over the substrate, and a magnetoresistive random-access memory (MRAM) cell electrically coupled to the TFT. The TFT includes a gate electrode; a gate dielectric layer disposed over the gate electrode; source/drain electrodes disposed above the gate electrode; and an active layer disposed above the gate electrode. A protection layer is disposed between the TFT and the MRAM cell and electrically connects the MRAM cell to the TFT.
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公开(公告)号：US12112784B2
公开(公告)日：2024-10-08
申请号：US17751898
申请日：2022-05-24
发明人： Sungchul Lee , Kyungjin Lee
CPC分类号： G11C11/161 , H10B61/00 , H10N50/10 , H10N50/80 , H10N50/85
摘要： A magneto resistive random access memory (MRAM) device including a spin orbit torque structure including a stack of an oxide layer pattern, a ferromagnetic pattern, and a non-magnetic pattern; and a magnetic tunnel junction (MTJ) structure on the spin orbit torque structure, the MTJ structure including a stack of a free layer pattern, a tunnel barrier pattern, and a pinned layer pattern, wherein the spin orbit torque structure extends in a first direction parallel to an upper surface of the spin orbit torque structure, the ferromagnetic pattern includes a horizontal magnetic material, and the free layer pattern has a magnetization direction in a vertical direction perpendicular to the upper surface of the spin orbit torque structure, the magnetization direction being changeable in response to spin currents generated in the spin orbit torque structure.
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