Invention Application
- Patent Title: VERTICAL 2-TRANSISTOR MEMORY CELL
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Application No.: US18662659Application Date: 2024-05-13
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Publication No.: US20240373619A1Publication Date: 2024-11-07
- Inventor: Kamal M. Karda , Srinivas Pulugurtha , Haitao Liu , Karthik Sarpatwari , Durai Vishak Nirmal Ramaswamy
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Main IPC: H10B12/00
- IPC: H10B12/00 ; G11C11/402

Abstract:
Some embodiments include apparatuses and methods of forming the apparatus. One of the apparatuses and methods includes a memory cell having a first transistor and a second transistor located over a substrate. The first transistor includes a channel region. The second transistor includes a channel region located over the channel region of the first transistor and electrically separated from the first channel region. The memory cell includes a memory element located on at least one side of the channel region of the first transistor. The memory element is electrically separated from the channel region of the first transistor, and electrically coupled to the channel of the second transistor.
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