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公开(公告)号：US12080359B2
公开(公告)日：2024-09-03
申请号：US18189824
申请日：2023-03-24
CPC分类号： G11C16/3404 , G11C16/10 , G11C16/26 , G11C16/30
摘要： Systems, methods and apparatus to determine a programming mode of a set of memory cells that store an indicator of the programming mode. In response to a command to read the memory cells in a memory device, a first read voltage is applied to the memory cells to identify a first subset of the memory cells that become conductive under the first read voltage. The determination of the first subset is configured as an operation common to different programming modes. Based on whether the first subset of the memory cell includes one or more predefined memory cells, the memory device determines a programming mode of memory cells. Once the programming mode is identified from the common operation, the memory device can further execute the command to determine a data item stored, via the programming mode, in the memory cells.
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2.发明公开公开(公告)号：US20240074138A1
公开(公告)日：2024-02-29
申请号：US18238269
申请日：2023-08-25
IPC分类号： H10B12/00
CPC分类号： H10B12/00
摘要： Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a first data line; a second data line adjacent the first data line and separated from the first data line by a first dielectric structure; and a memory cell formed over the first and second data lines. The memory cell includes a first transistor including a first channel region formed over and coupled to the first data line, and a charge storage structure separated from the first channel region; a second transistor including a second channel region formed over and coupled to the second data line, wherein the charge storage structure is formed over and coupled to the second channel region; and a second dielectric structure between the first channel region and each of the second channel region and the charge storage structure.
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公开(公告)号：US11791391B1
公开(公告)日：2023-10-17
申请号：US17655479
申请日：2022-03-18
发明人： Kamal M. Karda , Haitao Liu , Durai Vishak Nirmal Ramaswamy , Karthik Sarpatwari , Richard E. Fackenthal
IPC分类号： H01L29/423 , H01L27/02 , H01L27/092 , G11C5/02 , H10B10/00
CPC分类号： H01L29/42372 , G11C5/025 , H01L27/0207 , H01L27/092 , H10B10/12
摘要： An inverter includes a transistor, an additional transistor overlying the transistor, and a hybrid gate electrode interposed between and shared by the transistor and the additional transistor. The hybrid gate electrode includes a region overlying a channel structure of the transistor, an additional region overlying the region and underlying an additional channel structure of the additional transistor, and further region interposed between the region and the additional region. The region has a first material composition. The additional region has a second material composition different than the first material composition of the region. Memory devices and electronic systems are also described.
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公开(公告)号：US11775431B2
公开(公告)日：2023-10-03
申请号：US17556891
申请日：2021-12-20
发明人： Amitava Majumdar , Sandeep Krishna Thirumala , Lingming Yang , Karthik Sarpatwari , Nevil N. Gajera
IPC分类号： G06F12/08 , G06F12/0802
CPC分类号： G06F12/0802 , G06F2212/60 , G06F2212/72
摘要： This document describes apparatuses and techniques for cache memory with randomized eviction. In various aspects, a cache memory randomly selects a cache line for eviction and/or replacement. The cache memory may also support multi-occupancy whereby the cache memory enters data reused from another cache line to replace the data of the randomly evicted cache line. By so doing, the cache memory may operate in a nondeterministic fashion, which may increase a probability of data remaining in the cache memory for subsequent requests.
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公开(公告)号：US20230269922A1
公开(公告)日：2023-08-24
申请号：US18141046
申请日：2023-04-28
IPC分类号： H10B12/00 , G11C11/401
CPC分类号： H10B12/20 , G11C11/401
摘要： Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a substrate, a conductive plate located over the substrate to couple a ground connection, a data line located between the substrate and the conductive plate, a memory cell, and a conductive line. The memory cell includes a first transistor and a second transistor. The first transistor includes a first region electrically coupled between the data line and the conductive plate, and a charge storage structure electrically separated from the first region. The second transistor includes a second region electrically coupled to the charge storage structure and the data line. The conductive line is electrically separated from the first and second regions and spans across part of the first region of the first transistor and part of the second region of the second transistor and forming a gate of the first and second transistors.
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公开(公告)号：US20230178167A1
公开(公告)日：2023-06-08
申请号：US17545335
申请日：2021-12-08
CPC分类号： G11C29/42 , G11C29/4401 , G11C29/1201 , G11C29/12005 , G11C29/20
摘要： A memory device can include multiple memory cells and a processing device operatively coupled with the memory device to perform operations including grouping the memory cells into a groups based on a metric reflecting an electrical distance of a memory cell from a voltage source, and determining, for each group, a respective share of write operations, wherein the share of write operations is related to an aggregate value of the metric for memory cells of the group. The operations can also include distributing the write operations to each group according to the share of write operations determined for the group.
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公开(公告)号：US11631453B2
公开(公告)日：2023-04-18
申请号：US17545756
申请日：2021-12-08
IPC分类号： G11C11/00 , G11C11/4097 , G11C11/4096 , H01L27/108 , G11C11/4094
摘要： Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes multiple levels of two-transistor (2T) memory cells vertically arranged above a substrate. Each 2T memory cell includes a charge storage transistor having a gate, a write transistor having a gate, a vertically extending access line, and a single bit line pair. The source or drain region of the write transistor is directly coupled to a charge storage structure of the charge storage transistor. The vertically extending access line is coupled to gates of both the charge storage transistor and the write transistor of 2T memory cells in multiple respective levels of the multiple vertically arranged levels. The vertically extending access line and the single bit line pair are used for both write operations and read operations of each of the 2T memory cells to which they are coupled.
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公开(公告)号：US20230030585A1
公开(公告)日：2023-02-02
申请号：US17967441
申请日：2022-10-17
IPC分类号： H01L27/108 , G11C11/401
摘要： Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a first data line located in a first level of the apparatus; a second data line located in a second level of the apparatus; a first memory cell located in a third level of the apparatus between the first and second levels, the first memory cell including a first transistor coupled to the first data line, and a second transistor coupled between the first data line and a charge storage structure of the first transistor; and a second memory cell located in a fourth level of the apparatus between the first and second levels, the second memory cell including a third transistor coupled to the second data line, and a fourth transistor coupled between the second data line and a charge storage structure of the third transistor, the first transistor coupled in series with the third transistor between the first and second data lines.
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公开(公告)号：US11545194B2
公开(公告)日：2023-01-03
申请号：US17306562
申请日：2021-05-03
IPC分类号： G11C7/10
摘要： Methods, systems, and devices for dynamic read voltage techniques are described. In some examples, a memory device may include one or more partitions made up of multiple disjoint subsets of memory arrays. The memory device may receive a read command to read the one or more partitions and enter a drift determination phase. During the drift determination phase, the memory device may concurrently apply a respective voltage of a set of voltages to each disjoint subset and determine a quantity of memory cells in each disjoint subset that have a threshold voltage below the applied voltage. Based on a comparison between the determined quantity of memory cells and a predetermined quantity of memory cells, the memory device may select a voltage from the set of voltages and utilize the selected voltage to read the one or more partitions.
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公开(公告)号：US20220392535A1
公开(公告)日：2022-12-08
申请号：US17336913
申请日：2021-06-02
发明人： Karthik Sarpatwari , Nevil N. Gajera , Lingming Yang , Yen Chun Lee , Jessica Chen , Francesco Douglas Verna-Ketel
摘要： Systems, methods and apparatus to program memory cells to an intermediate state. A first voltage pulse is applied in a first polarity across each respective memory cell among the memory cells to move its threshold voltage in the first polarity to a first voltage region representative of a first value. A second voltage pulse is then applied in a second polarity to further move its threshold voltage in the first polarity to a second voltage region representative of a second value and the intermediate state. A magnitude of the second voltage pulse applied for the memory cells is controlled by increasing the magnitude in increments until the memory cells are sensed to be conductive. Optionally, prior to the first voltage pulse, a third voltage pulse is applied in the second polarity to cancel or reduce a drift in threshold voltages of the respective memory cell.
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