A semiconductor memory device includes a substrate; a first dielectric layer on the substrate; and bottom electrodes on the first dielectric layer. The bottom electrodes are arranged equidistantly in a first direction and extend along a second direction. A second dielectric layer is disposed on the first dielectric layer. Top electrodes are disposed in the second dielectric layer and arranged at intervals along the second direction. Each top electrode includes a lower portion located around each bottom electrode and a tapered upper portion. A third dielectric layer is disposed above the bottom electrodes and around the tapered upper portion. A resistive-switching layer is disposed between a sidewall of each bottom electrode and a sidewall of the lower portion and between the third dielectric layer and a sidewall of the tapered upper portion. An air gap is disposed in the third dielectric layer.