Invention Application
- Patent Title: SORT-TOP RASTERIZATION AND TILE RENDERING USING AN ACCELERATION STRUCTURE
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Application No.: US18205407Application Date: 2023-06-02
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Publication No.: US20240404176A1Publication Date: 2024-12-05
- Inventor: Christopher J. Brennan
- Applicant: ADVANCED MICRO DEVICES, INC.
- Applicant Address: US CA Santa Clara
- Assignee: ADVANCED MICRO DEVICES, INC.
- Current Assignee: ADVANCED MICRO DEVICES, INC.
- Current Assignee Address: US CA Santa Clara
- Main IPC: G06T15/20
- IPC: G06T15/20 ; G06T1/20 ; G06T17/20

Abstract:
To render a scene in a display space, a processor is configured to perform sort-top tiled rendering. To this end, the processor is configured to divide a display space into two or more tiles and assign each tile to a respective graphics core of the processor. Further, the processor is configured to divide a viewport of the scene into corresponding frustums each representing a portion of the viewport in a respective tile. Using a corresponding frustum associated with an assigned tile, each graphics core performs one or more frustum queries to determine one or more graphics objects in a tile to rasterize, one or more draw calls to perform for a tile, or both.
Information query