A processor employs a hardware signal monitor to manage signaling for accelerators. The hardware signal monitor monitors designated memory addresses assigned to accelerator signals. In response to a memory write to one of the designated memory addresses, the hardware signal monitor executes a set of one or more operations (referred to as a callback). The hardware signal monitor thereby enables improved and enhanced signaling features, such as asynchronous signaling between agents, inter-accelerator signaling, and inter-process signaling.