A memory device (e.g., a high-bandwidth memory (HBM) device) with multiple physical interfaces (PHYs) is disclosed. The memory device includes a base semiconductor die having a first physical interface (PHY) arranged in accordance with a Joint Electron Device Engineering Council (JEDEC) standard and a second PHY arranged differently from the first PHY and electrically disconnected from the first PHY. The base semiconductor die further includes first contacts disposed at a first side of the base semiconductor die and second contacts disposed at a second side of the base semiconductor die opposite the first side. The first contacts and the second contacts couple with a first one of the first PHY and the second PHY. The memory device further includes one or more memory dies coupled with the base semiconductor die through the second contacts.