A memory device includes a cell array including a plurality of static random-access memory (SRAM) cells; a row decoder configured to drive a plurality of word lines of the plurality of SRAM cells based on a row address; a data input/output circuit connected to a plurality of bit lines of the cell array and connected to a sub-power line configured to supply cell voltage to the plurality of SRAM cells; and a word line pulse generator configured to generate a word line pulse with a first pulse width that varies based on the row address and to provide the word line pulse to the row decoder.