Invention Application
- Patent Title: CAPACITANCE BALANCING IN SEMICONDUCTOR DEVICES
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Application No.: US18788001Application Date: 2024-07-29
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Publication No.: US20250095718A1Publication Date: 2025-03-20
- Inventor: Eric Carman , Christopher Morzano
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Main IPC: G11C11/4091
- IPC: G11C11/4091 ; G11C11/408 ; G11C11/4094

Abstract:
Systems, methods, and apparatus are provided for capacitance balancing in semiconductor devices. An apparatus comprising a sense amplifier having first and second nodes and configured to amplify a voltage difference between the first and second nodes. A first global sense line is coupled to the first node and a plurality of first locals sense lines are coupled in parallel to the first global sense line. A second global sense line is coupled to the second node and a plurality of second local sense lines are coupled in parallel to the second global sense line. Control circuitry is configured to electrically connect the selected first local sense line of the plurality of first local sense lines to the first global sense line and electrically connect at least two second local sense lines of the plurality of second local sense lines to the second global sense line.
Information query
IPC分类: