公开(公告)号：US20250037756A1

公开(公告)日：2025-01-30

申请号：US18791706

申请日：2024-08-01

Applicant: Micron Technology, Inc.

Inventor： Eric Carman ,  Daniele Vimercati

IPC: G11C11/4091 ,  G11C7/06 ,  G11C11/4074 ,  G11C11/4094 ,  G11C11/4096 ,  G11C11/4099

Abstract: Methods, systems, and devices for sense amplifier with digit line multiplexing are described. A method includes precharging an input and an output of an amplifier stage of a sense component to a first voltage based on a read operation associated with a memory cell. The method includes precharging a first side and a second side of a latch stage of the sense component to the first voltage based on precharging the output of the amplifier stage to the first voltage, the latch stage coupled with the amplifier stage. The method may also include coupling a second voltage from a digit line associated with the memory cell to the input of the amplifier stage, the amplifier stage generating a third voltage on the output based on coupling the second voltage to the input, and the latch stage latching a logic value associated with the memory cell based on the third voltage.

公开(公告)号：US12073870B2

公开(公告)日：2024-08-27

申请号：US18217205

申请日：2023-06-30

Applicant: Micron Technology, Inc.

Inventor： Eric Carman ,  Daniele Vimercati

IPC: G11C7/06 ,  G11C11/4074 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096 ,  G11C11/4099

CPC classification number: G11C11/4091 ,  G11C7/065 ,  G11C11/4074 ,  G11C11/4094 ,  G11C11/4096 ,  G11C11/4099

Abstract: Methods, systems, and devices for sense amplifier with digit line multiplexing are described. A method includes precharging an input and an output of an amplifier stage of a sense component to a first voltage based on a read operation associated with a memory cell. The method includes precharging a first side and a second side of a latch stage of the sense component to the first voltage based on precharging the output of the amplifier stage to the first voltage, the latch stage coupled with the amplifier stage. The method may also include coupling a second voltage from a digit line associated with the memory cell to the input of the amplifier stage, the amplifier stage generating a third voltage on the output based on coupling the second voltage to the input, and the latch stage latching a logic value associated with the memory cell based on the third voltage.

公开(公告)号：US20210398576A1

公开(公告)日：2021-12-23

申请号：US17466655

申请日：2021-09-03

Applicant: Micron Technology, Inc.

Inventor： Eric Carman

IPC: G11C7/22 ,  G11C7/06 ,  G06F13/16 ,  G11C11/4093 ,  G11C16/26

Abstract: Methods, systems, and devices for timing chains for accessing memory cells are described to implement some delays at logic circuitry under an array of memory cells. The memory array logic may represent CMOS under array logic circuitry. A bank group logic may generate a first memory operation and a longer delay corresponding to a timing between the first operation and a second operation. The first operation may represent an access operation, a precharging operation, or the like. The memory array logic may be signaled regarding the first operation and may generate one or more smaller delays associated with one or more sub-operations of the first operation. The smaller delays may be tunable, which may support a memory device or controller to implement operations or sub-operations with different timings based on different processes, different memory cell characteristics, or different temperatures, among other examples.

公开(公告)号：US09679612B2

公开(公告)日：2017-06-13

申请号：US14789453

申请日：2015-07-01

Applicant: Micron Technology, Inc.

Inventor： Eric Carman

IPC: H01L27/102 ,  G11C5/02 ,  H01L27/108 ,  H01L29/73 ,  H01L29/78 ,  G11C11/402 ,  G11C16/26 ,  G11C5/06 ,  G11C7/00

CPC classification number: G11C5/02 ,  G11C5/06 ,  G11C7/00 ,  G11C11/402 ,  G11C16/26 ,  H01L27/1023 ,  H01L27/10802 ,  H01L29/73 ,  H01L29/7841

Abstract: Techniques for providing a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a direct injection semiconductor memory device including a first region coupled to a source line, a second region coupled to a bit line. The direct injection semiconductor memory device may also include a body region spaced apart from and capacitively coupled to a word line, wherein the body region is electrically floating and disposed between the first region and the second region. The direct injection semiconductor memory device may further include a third region coupled to a carrier injection line configured to inject charges into the body region through the second region.

公开(公告)号：US20250095718A1

公开(公告)日：2025-03-20

申请号：US18788001

申请日：2024-07-29

Applicant: Micron Technology, Inc.

Inventor： Eric Carman ,  Christopher Morzano

IPC: G11C11/4091 ,  G11C11/408 ,  G11C11/4094

Abstract: Systems, methods, and apparatus are provided for capacitance balancing in semiconductor devices. An apparatus comprising a sense amplifier having first and second nodes and configured to amplify a voltage difference between the first and second nodes. A first global sense line is coupled to the first node and a plurality of first locals sense lines are coupled in parallel to the first global sense line. A second global sense line is coupled to the second node and a plurality of second local sense lines are coupled in parallel to the second global sense line. Control circuitry is configured to electrically connect the selected first local sense line of the plurality of first local sense lines to the first global sense line and electrically connect at least two second local sense lines of the plurality of second local sense lines to the second global sense line.

公开(公告)号：US11727981B2

公开(公告)日：2023-08-15

申请号：US17369873

申请日：2021-07-07

Applicant: Micron Technology, Inc.

Inventor： Eric Carman ,  Daniele Vimercati

IPC: G11C7/12 ,  G11C11/4091 ,  G11C11/4074 ,  G11C7/06 ,  G11C11/4094 ,  G11C11/4099 ,  G11C11/4096

CPC classification number: G11C11/4091 ,  G11C7/065 ,  G11C11/4074 ,  G11C11/4094 ,  G11C11/4096 ,  G11C11/4099

Abstract: Methods, systems, and devices for sense amplifier with digit line multiplexing are described. A method includes precharging an input and an output of an amplifier stage of a sense component to a first voltage based on a read operation associated with a memory cell. The method includes precharging a first side and a second side of a latch stage of the sense component to the first voltage based on precharging the output of the amplifier stage to the first voltage, the latch stage coupled with the amplifier stage. The method may also include coupling a second voltage from a digit line associated with the memory cell to the input of the amplifier stage, the amplifier stage generating a third voltage on the output based on coupling the second voltage to the input, and the latch stage latching a logic value associated with the memory cell based on the third voltage.

公开(公告)号：US11574665B2

公开(公告)日：2023-02-07

申请号：US17466655

申请日：2021-09-03

Applicant: Micron Technology, Inc.

Inventor： Eric Carman

IPC: G11C7/22 ,  G11C7/06 ,  G06F13/16 ,  G11C11/4093 ,  G11C16/26

Abstract: Methods, systems, and devices for timing chains for accessing memory cells are described to implement some delays at logic circuitry under an array of memory cells. The memory array logic may represent CMOS under array logic circuitry. A bank group logic may generate a first memory operation and a longer delay corresponding to a timing between the first operation and a second operation. The first operation may represent an access operation, a precharging operation, or the like. The memory array logic may be signaled regarding the first operation and may generate one or more smaller delays associated with one or more sub-operations of the first operation. The smaller delays may be tunable, which may support a memory device or controller to implement operations or sub-operations with different timings based on different processes, different memory cell characteristics, or different temperatures, among other examples.

公开(公告)号：US20230011345A1

公开(公告)日：2023-01-12

申请号：US17369873

申请日：2021-07-07

Applicant: Micron Technology, Inc.

Inventor： Eric Carman ,  Daniele Vimercati

IPC: G11C11/4091 ,  G11C11/4074 ,  G11C11/4096 ,  G11C11/4094 ,  G11C11/4099 ,  G11C7/06

Abstract: Methods, systems, and devices for sense amplifier with digit line multiplexing are described. A method includes precharging an input and an output of an amplifier stage of a sense component to a first voltage based on a read operation associated with a memory cell. The method includes precharging a first side and a second side of a latch stage of the sense component to the first voltage based on precharging the output of the amplifier stage to the first voltage, the latch stage coupled with the amplifier stage. The method may also include coupling a second voltage from a digit line associated with the memory cell to the input of the amplifier stage, the amplifier stage generating a third voltage on the output based on coupling the second voltage to the input, and the latch stage latching a logic value associated with the memory cell based on the third voltage.

公开(公告)号：US09767880B1

公开(公告)日：2017-09-19

申请号：US15071991

申请日：2016-03-16

Applicant: Micron Technology, Inc.

Inventor： Eric Carman

IPC: G11C11/22

CPC classification number: G11C11/2275 ,  G11C11/221 ,  G11C11/2293

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. Prior to writing a logic value to a ferroelectric memory cell, a digit line of a ferroelectric memory cell may be biased to a first voltage, and a cell plate of the ferroelectric memory cell may be biased to a second voltage. A magnitude of a difference between the first voltage and the second voltage may be greater than a magnitude of a write voltage for the first ferroelectric memory cell. The magnitude of the difference between the first voltage and the second voltage may decrease the time to reach a write voltage for the ferroelectric memory cell. Several example cell plate drivers are also disclosed.

公开(公告)号：US20230395131A1

公开(公告)日：2023-12-07

申请号：US17860470

申请日：2022-07-08

Applicant: Micron Technology, Inc.

Inventor： Eric Carman

IPC: G11C11/4091

CPC classification number: G11C11/4091

Abstract: Sense amplifiers for memory devices include latch transistors that are used to latch values based on charges in memory cells. A first latch transistor applies a reference voltage to a first gut node of the sense amplifier via one of these latch transistors. The sense amplifier also applies a charge to a second gut node from a memory cell corresponding to the sense amplifier. The sense amplifier also latches a value in the sense amplifier based on a relationship between the reference voltage and the charge.