Invention Application
- Patent Title: INTEGRATED CIRCUIT DEVICES INCLUDING LOWER INTERCONNECT METAL LAYERS AT CELL BOUNDARIES AND METHODS OF FORMING THE SAME
-
Application No.: US18752851Application Date: 2024-06-25
-
Publication No.: US20250105153A1Publication Date: 2025-03-27
- Inventor: Jintae Kim , Panjae Park , Kang-Ill Seo
- Applicant: Samsung Electronics Co., Ltd.
- Applicant Address: KR Suwon-si
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Suwon-si
- Main IPC: H01L23/528
- IPC: H01L23/528 ; H01L23/48 ; H01L27/092

Abstract:
Integrated circuit devices are provided. An integrated circuit device includes a substrate and a cell that has a plurality of transistors. The transistors include an upper transistor having an upper channel region. Moreover, the transistors include a lower transistor between the substrate and the upper transistor. The lower transistor includes a lower channel region. The integrated circuit device includes a power line extending longitudinally in a first horizontal direction below the substrate and defining a cell boundary of the cell that extends longitudinally in the first horizontal direction. The integrated circuit device includes a cell boundary signal metal pattern on the cell and extending longitudinally in the first horizontal direction over the cell boundary and connected to at least two transistors of the plurality of transistors. Related methods of forming integrated circuit devices are also provided.
Information query
IPC分类: