公开(公告)号：US11699992B2

公开(公告)日：2023-07-11

申请号：US16726379

申请日：2019-12-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jintae Kim ,  Byounggon Kang ,  Changbeom Kim ,  Ha-Young Kim ,  Yongeun Cho

IPC: H03K3/037 ,  H01L27/02 ,  H01L23/528 ,  H01L29/06 ,  H01L27/092 ,  H01L23/522 ,  H01L29/423

CPC classification number: H03K3/0372 ,  H01L23/5226 ,  H01L23/5286 ,  H01L27/0207 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/42392

Abstract: A semiconductor device includes a flip flop cell. The flip flop cell is formed on a semiconductor substrate, includes a flip flop circuit, and comprises a scan mux circuit, a master latch circuit, a slave latch circuit, a clock driver circuit, and an output circuit. Each of the scan mux circuit, the master latch circuit, the slave latch circuit, the clock driver circuit, and the output circuit includes a plurality of active devices which together output a resulting signal for that circuit based on inputs, is a sub-circuit of the flip flop circuit, and occupies a continuously-bounded area of the flip flop circuit from a plan view. At least a first sub-circuit and a second sub-circuit of the sub-circuits overlap from the plan view in a first overlap region, the first overlap region including part of a first continuously-bounded area for the first sub-circuit and part of a second continuously-bounded area for the second sub-circuit.

公开(公告)号：US20220189945A1

公开(公告)日：2022-06-16

申请号：US17545009

申请日：2021-12-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeha Lee ,  Jintae Kim ,  Keunho Lee ,  Dongyeon Heo

IPC: H01L27/02 ,  G06F30/392

Abstract: An integrated circuit includes: a first cell arranged in a first row extending in a first direction and performing a first function, a second cell arranged in the first row and performing a second function, a third cell arranged in a second row extending in the first direction and performing the first function, a fourth cell arranged in the second row and performing the second function, a first connection line connecting a first via in the first cell to a second via in the second cell, and a second connection line connecting a third via in the third cell to a fourth via in the fourth cell, wherein a length of the first connection line is different from a length of the second connection line.

公开(公告)号：US20210343699A1

公开(公告)日：2021-11-04

申请号：US17147567

申请日：2021-01-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jintae Kim ,  Jaeha Lee ,  Dongyeon Heo

IPC: H01L27/02 ,  H01L23/522 ,  H01L23/528 ,  H01L29/08 ,  H01L29/417 ,  H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  G06F30/394

Abstract: A semiconductor device includes first and second standard cells having respective semiconductor elements and first interconnection lines electrically connected to the semiconductor elements, on a substrate. A routing structure is provided, which is disposed on the first and second standard cells. The routing structure includes second interconnection lines electrically connected to the first interconnection lines. The first interconnection lines include a first power transmission line, which is configured to supply power to a semiconductor element, and a first signal transmission line electrically coupled to a semiconductor element. The second interconnection lines include: (i) a second power transmission line electrically connected to the first power transmission line and extending by a first length, (ii) a second signal transmission line electrically connected to the first signal transmission line, and (iii) a staple line electrically connected to the first power transmission line, extending on a boundary between the first and second standard cells, and extending by a second length, less than the first length.

公开(公告)号：US20170117898A1

公开(公告)日：2017-04-27

申请号：US15285348

申请日：2016-10-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dalhee Lee ,  Jintae Kim ,  Jaeha Lee

IPC: H03K19/0185

CPC classification number: H03K19/018521

Abstract: A level shifting circuit includes a level shifting portion configured to receive an input signal and generate an output signal, and a current adjustment circuit connected between the level shifting portion and a drive high voltage node at which a drive high voltage is applied. The current adjustment circuit is configured to adjust an amount of current provided from the drive high voltage node to the level shifting portion.

公开(公告)号：US20250105153A1

公开(公告)日：2025-03-27

申请号：US18752851

申请日：2024-06-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jintae Kim ,  Panjae Park ,  Kang-Ill Seo

IPC: H01L23/528 ,  H01L23/48 ,  H01L27/092

Abstract: Integrated circuit devices are provided. An integrated circuit device includes a substrate and a cell that has a plurality of transistors. The transistors include an upper transistor having an upper channel region. Moreover, the transistors include a lower transistor between the substrate and the upper transistor. The lower transistor includes a lower channel region. The integrated circuit device includes a power line extending longitudinally in a first horizontal direction below the substrate and defining a cell boundary of the cell that extends longitudinally in the first horizontal direction. The integrated circuit device includes a cell boundary signal metal pattern on the cell and extending longitudinally in the first horizontal direction over the cell boundary and connected to at least two transistors of the plurality of transistors. Related methods of forming integrated circuit devices are also provided.

公开(公告)号：US20250063811A1

公开(公告)日：2025-02-20

申请号：US18593051

申请日：2024-03-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Panjae Park ,  Jintae Kim ,  Kang-ill Seo

IPC: H01L27/092 ,  H01L21/822 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

Abstract: An integrated circuit device includes a wimpy transistor stack and a reference transistor stack on a substrate. The wimpy transistor stack may include a first intergate insulator that is thicker than a second intergate insulator of the reference transistor stack. Due to the thicker first intergate insulator, a number of first upper channel regions of the wimpy transistor stack may be less than a number of second upper channel regions of reference transistor stack, and/or a number of first lower channel regions of the wimpy transistor stack may be less than a number of second lower channel regions of the reference transistor stack.

公开(公告)号：US09779198B2

公开(公告)日：2017-10-03

申请号：US14832307

申请日：2015-08-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daekwon Kang ,  Donggyun Kim ,  Jaeseok Yang ,  Jiyoung Jung ,  Chunghee Kim ,  Ha-Young Kim ,  Sungkeun Park ,  Younggook Park ,  Myungsoo Jang ,  Jintae Kim

IPC: G06F17/50 ,  G03F1/70

CPC classification number: G06F17/5072 ,  G03F1/36 ,  G03F1/70 ,  G06F17/5068 ,  G06F17/5081

Abstract: A method can include separating a design area of a substrate for a semiconductor integrated circuit (IC) into cell blocks, where a distance between adjacent ones of the cell blocks can be greater than or equal to a minimum distance defined by a design rule for the semiconductor integrated circuit to provide separated cell blocks, designing a layout for the semiconductor IC in the separated cell blocks, and individually coloring the layout of each of the separated cell blocks.

公开(公告)号：US09496179B2

公开(公告)日：2016-11-15

申请号：US14833922

申请日：2015-08-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Ho Do ,  Sanghoon Baek ,  Sunyoung Park ,  Sang-Kyu Oh ,  Jintae Kim ,  Hyosig Won

IPC: H01L21/768 ,  H01L21/8234 ,  H01L21/027 ,  H01L21/321

CPC classification number: H01L21/823475 ,  H01L21/0274 ,  H01L21/28008 ,  H01L21/32115 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L29/41758 ,  H01L29/66568

Abstract: A method of manufacturing a semiconductor device includes forming an active pattern and a gate electrode crossing the active pattern on a substrate, forming a first contact connected to the active pattern at a side of the gate electrode, forming a second contact connected to the gate electrode, and forming a third contact connected to the first contact at the side of the gate electrode. The third contact is formed using a photomask different from that used to form the first contact. A bottom surface of the third contact is disposed at a level in the device lower than the level of a top surface of the first contact.

Abstract translation: 一种制造半导体器件的方法包括：在基板上形成与有源图案交叉的有源图案和栅电极，在栅电极侧形成连接到有源图案的第一触点，形成连接到栅电极的第二触点 并且形成在栅电极侧与第一接触连接的第三触点。 使用不同于用于形成第一接触的光掩模形成第三接触。 第三触点的底表面设置在低于第一触点的顶表面的高度的装置中的水平面上。

公开(公告)号：US11798933B2

公开(公告)日：2023-10-24

申请号：US17147567

申请日：2021-01-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jintae Kim ,  Jaeha Lee ,  Dongyeon Heo

IPC: H01L23/528 ,  H01L23/522 ,  G06F30/394 ,  H01L27/02 ,  H01L29/08 ,  H01L29/417 ,  H01L29/78 ,  H01L29/423 ,  H01L29/786 ,  H01L29/06 ,  G06F30/396 ,  G06F30/392

CPC classification number: H01L27/0207 ,  G06F30/394 ,  H01L23/5226 ,  H01L23/5286 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/41733 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/7851 ,  H01L29/78618 ,  H01L29/78696 ,  G06F30/392 ,  G06F30/396

Abstract: A semiconductor device includes first and second standard cells having respective semiconductor elements and first interconnection lines electrically connected to the semiconductor elements, on a substrate. A routing structure is provided, which is disposed on the first and second standard cells. The routing structure includes second interconnection lines electrically connected to the first interconnection lines. The first interconnection lines include a first power transmission line, which is configured to supply power to a semiconductor element, and a first signal transmission line electrically coupled to a semiconductor element. The second interconnection lines include: (i) a second power transmission line electrically connected to the first power transmission line and extending by a first length, (ii) a second signal transmission line electrically connected to the first signal transmission line, and (iii) a staple line electrically connected to the first power transmission line, extending on a boundary between the first and second standard cells, and extending by a second length, less than the first length.

公开(公告)号：US11790146B2

公开(公告)日：2023-10-17

申请号：US17324829

申请日：2021-05-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaeha Lee ,  Jintae Kim ,  Seunghyun Yang ,  Dongyeon Heo

IPC: G06F30/392 ,  G06F30/398 ,  G06F30/394

CPC classification number: G06F30/392 ,  G06F30/394 ,  G06F30/398

Abstract: A semiconductor device including a standard cell is provided. The standard cell includes an active region; a gate structure intersecting the active region; a first conductive structure including: a first power supply line and a second power supply line; and a second conductive structure disposed on the first conductive structure, the second conductive structure including: first power distribution patterns spaced apart from each other a first boundary and electrically connected to the first power supply line, second power distribution patterns spaced apart from each other along a second boundary and electrically connected to the second power supply line, net metal lines disposed between and spaced apart from the first power distribution patterns and the second power distribution patterns, and electrically connected to a first portion of the signal lines, and pin metal lines electrically connected to a second portion of the signal lines.