A semiconductor package includes a cover layer including a first surface contacting a lower chip structure and a second surface opposite to the first surface. The lower chip structure includes one or more stacked chips. The one or more stacked chips contact the first surface of the cover layer and include an upper surface having groove. The cover layer includes convex portions on the first surface that fill the grooves, and one or more concave portions on the second surface that are aligned on one or more convex portions.