公开(公告)号：US20240222217A1

公开(公告)日：2024-07-04

申请号：US18593381

申请日：2024-03-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunjae KIM ,  Eunsil KANG ,  Daehyun KIM ,  Sunkyoung SEO

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/29 ,  H01L23/498 ,  H01L25/065 ,  H01L25/18 ,  H01L21/56

CPC classification number: H01L23/3192 ,  H01L23/295 ,  H01L23/3128 ,  H01L23/3185 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/17 ,  H01L24/73 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/18 ,  H01L21/561 ,  H01L24/02 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/02331 ,  H01L2224/02372 ,  H01L2224/02381 ,  H01L2224/0557 ,  H01L2224/06519 ,  H01L2224/13024 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2224/17519 ,  H01L2224/2929 ,  H01L2224/29386 ,  H01L2224/29499 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/06589 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161

Abstract: A semiconductor package includes a first semiconductor chip on a wiring structure, a plurality of internal terminals between the wiring structure and the first semiconductor chip; a high thermal conductivity layer is between the wiring structure and the first semiconductor chip; and an encapsulator on the high thermal conductivity layer and contacting the second semiconductor chip. Sidewalls of at least the wiring structure and the encapsulator are substantially coplanar.

公开(公告)号：US20230254975A1

公开(公告)日：2023-08-10

申请号：US18079267

申请日：2022-12-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunjae KIM ,  Kyongsoon CHO

IPC: H05K1/18 ,  H05K1/02

CPC classification number: H05K1/183 ,  H05K1/0274 ,  H05K2201/09036 ,  H05K2201/09427 ,  H05K2201/10121 ,  H05K2201/10628 ,  H05K2201/10977

Abstract: A semiconductor package that includes a circuit board having an opening therein. The circuit board includes a first portion, and a second portion disposed below the first portion. The first portion protrudes further in a horizontal direction towards the opening than the second portion. A transparent substrate is disposed on the circuit board. An image sensor chip is mounted on the circuit board. The image sensor chip includes an active array region facing the transparent substrate. A connection terminal directly contacts a lower surface of the first portion of the circuit board and an upper surface of the image sensor chip. A gap-fill member covers the connection terminal and covers a portion of an upper surface of the image sensor chip and at least a portion of a lateral side surface of the image sensor chip. The transparent substrate has a greater horizontal width than the circuit board.

公开(公告)号：US20240096841A1

公开(公告)日：2024-03-21

申请号：US18456261

申请日：2023-08-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ohguk KWON ,  Sunjae KIM ,  Seunghoon YEON ,  Seungryong OH ,  Huiyeong JANG

IPC: H01L23/00 ,  H01L21/66 ,  H01L25/065

CPC classification number: H01L24/32 ,  H01L22/32 ,  H01L24/16 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/26145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/3841

Abstract: A semiconductor package includes a first semiconductor chip including a first substrate, a plurality of through electrodes penetrating the first substrate, and first bonding pads provided on one surface of the first substrate and electrically connected to the plurality of through electrodes, a second semiconductor chip including a second substrate, a second wiring layer provided on one surface of the second substrate and having redistribution pads and test pads, and second bonding pads on the redistribution pads, the second semiconductor chip being stacked on the first semiconductor chip via conductive bumps that are disposed between first and second bonding pads, an adhesive layer filling a space between the conductive bumps, and flow prevention structures in the adhesive layer on a test pad region where the test pads are disposed.

公开(公告)号：US20230085734A1

公开(公告)日：2023-03-23

申请号：US17728275

申请日：2022-04-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunjae KIM ,  Chungho SONG ,  Yonghoe CHO

IPC: H01L27/146 ,  H01L23/00

Abstract: An image sensor package includes: a package base substrate having a cavity extending inwards from an upper surface thereof, and including a plurality of upper surface connection pads and a plurality of lower surface connection pads; an image sensor chip in the cavity, and including a chip body having a first surface and a second surface facing each other, a sensor unit located in the first surface of the chip body, and a plurality of chip pads around the sensor unit; a filter glass above the image sensor chip, and including a transparent substrate and a plurality of redistribution patterns on a lower surface of the transparent substrate; and a plurality of connection terminals between the plurality of redistribution patterns and the plurality of chip pads and between the plurality of redistribution patterns and the plurality of upper surface connection pads.

公开(公告)号：US20220173008A1

公开(公告)日：2022-06-02

申请号：US17332471

申请日：2021-05-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunjae KIM ,  Eunsil KANG ,  Daehyun KIM ,  Sunkyoung SEO

IPC: H01L23/31 ,  H01L25/18 ,  H01L25/065 ,  H01L23/29 ,  H01L23/498 ,  H01L23/00

Abstract: A semiconductor package includes a first semiconductor chip on a wiring structure, a plurality of internal terminals between the wiring structure and the first semiconductor chip; a high thermal conductivity layer is between the wiring structure and the first semiconductor chip; and an encapsulator on the high thermal conductivity layer and contacting the second semiconductor chip. Sidewalls of at least the wiring structure and the encapsulator are substantially coplanar.