Invention Grant
US3449555A Parallel binary to binary coded decimal and binary coded decimal to binary converter utilizing cascaded logic blocks
失效
二进制编码二进制和二进制编码二进制到二进制转换器利用逻辑逻辑块
- Patent Title: Parallel binary to binary coded decimal and binary coded decimal to binary converter utilizing cascaded logic blocks
- Patent Title (中): 二进制编码二进制和二进制编码二进制到二进制转换器利用逻辑逻辑块
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Application No.: US3449555DApplication Date: 1965-06-02
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Publication No.: US3449555APublication Date: 1969-06-10
- Inventor: WANG AN
- Applicant: WANG LABORATORIES
- Assignee: Wang Laboratories
- Current Assignee: Wang Laboratories
- Priority: US46064965 1965-06-02
- Main IPC: H03M7/12
- IPC: H03M7/12 ; G06F5/02 ; H03K13/00 ; H04L3/00
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