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公开(公告)号：US3511974A
公开(公告)日：1970-05-12
申请号：US3511974D
申请日：1966-03-22
Applicant: WANG LABORATORIES
Inventor： WANG AN
IPC: G06F3/08 , G06F7/48 , G06F7/498 , G06F7/556 , G06F9/302 , G06F9/40 , G06F15/02 , G11C17/00 , G06K7/01
CPC classification number: G06F7/498 , G06F3/08 , G06F7/556 , G06F9/3001 , G06F9/4425 , G06F15/02 , G11C17/00
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公开(公告)号：US3872959A
公开(公告)日：1975-03-25
申请号：US33148673
申请日：1973-02-12
Applicant: WANG LABORATORIES
Inventor： WANG AN , CHU GE YAO , WU EDWARD S
CPC classification number: B41J19/96 , B41J5/30 , B41J19/32 , B41J25/20 , Y10S400/903
Abstract: A writer selectively operable in an alpha-numric symbol printing mode and a positioning mode. The writer includes a horizontally movable type head having a plurality of corresponding alphanumeric printing symbols, operable in response to printing signals to print the symbols and horizontally movable in response to horizontal spacing function signals; and a platen rotatable in response to vertical spacing function signals. Type head drive means are provided for incrementally horizontally moving the type head in fine increments, the alpha-numeric spacing increments being an integral multiple thereof, and platen drive means are provided for incrementally rotating the platen in fine increments. In general, this is done by control means for operating the type head comprising horizontal function signal generating means for incrementally horizontally moving the type head in fine increments, and platen drive means comprising vertical function signal generating means for incrementally rotating the platen in fine increments, the function keys providing function signals being connected to the function signal generating means for generating a plurality of fine increment signals equal to an alpha-numeric increment.
Abstract translation: 写入器可选择性地以阿尔法数字符号打印模式和定位模式操作。 作者包括具有多个对应的字母数字打印符号的水平移动型头部，可响应于打印信号打印符号并响应于水平间隔功能信号而水平移动; 以及可以响应于垂直间隔功能信号而旋转的压板。 提供类型头驱动装置用于以微小的增量递增地水平移动类型头，字母数字间距增量是其整数倍，并且提供压板驱动装置用于以微小的增量递增地旋转压板。 通常，这通过用于操作类型头的控制装置来实现，该类型头包括水平功能信号产生装置，用于以微小增量递增地水平移动类型头部;以及压板驱动装置，其包括垂直功能信号发生装置，用于以微小的增量递增地旋转压板， 提供功能信号的功能键连接到功能信号产生装置，用于产生等于字母数字增量的多个精细增量信号。
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3.发明授权Parallel binary to binary coded decimal and binary coded decimal to binary converter utilizing cascaded logic blocks 失效二进制编码二进制和二进制编码二进制到二进制转换器利用逻辑逻辑块
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Patent Agency Ranking
公开(公告)号：US3509329A
公开(公告)日：1970-04-28
申请号：US3509329D
申请日：1966-10-24
Applicant: WANG LABORATORIES
Inventor： WANG AN , ROBINSON PRENTICE IRVING
CPC classification number: G06F9/3001 , G06F3/0227 , G06F7/556 , G06F9/4425 , G06F15/02 , G09G3/04
Abstract: 1,199,022. Digital electric calculator. WANG LABORATORIES Inc. 19 Sept., 1967 [24 Oct., 1966], No. 42603/67. Heading G4A. A calculator comprises a keyboard having keys representing digits 0 to 9 and instructions arranged to produce a code unique to each key, two independently controllable accumulator storage registers, each storing numerical values, a unit displaying the contents of one of the registers, an arithmetic unit performing addition and subtraction upon operands ranging in value from 0 to 9, a store of logarithmic constant values and associated means for addressing and reading out of the store selected ones of the constant values, and a control unit including a source of clock pulses, a cycle control and subsidiary control elements and arranged to control the operation of the storage registers, the arithmetic unit and the store of logarithmic constant values in response to the instruction codes. General.-The keyboard enables entry of digits, control of arithmetic operations, the performance of the operations e x , loge X, #X and X 2 to be performed and various operations of clearing and recalling from appropriate registers to be performed. A core memory holds Work register W, Right and Left Accumulator registers A 0 , A 1 and a log register L. Digits from the keyboard are entered in the Work register and automatically displayed. Operation of the log X key causes generation of the natural log of the number in the Work register, the log being stored in the log register and this value is then entered in the Work register. The e x key causes generation of the antilog of the number which is then stored in the Work register. An ENTER key causes the logs of digits entered to be held in the log register, successive logs being added and the antilog of the result being generated when the a X= key is pressed and stored in the Work register. The core registers each hold 16 b.c.d. digits, the least significant digit holding the decimal point position, the most s.d. holding the sign. Only 10 of the 14 digits of the number are displayed on the screen. Each digit can be individually addressed and arithmetic operations are done serially, each digit being treated in parallel, the particular digit being operated on being determined by an R or a T counter. A D-switch determines the source of data read to the memory. A digit read out of the memory is initially stored in an E register and may be transferred to a G register, display, the adder or back to the memory. The arithmetic unit is supplied with one operand from the E register and the other from a source determined by the B switch. Each digit received by the B switch is applied to a 9's complement matrix enabled if subtraction operations are required. The sum from the adder is applied to a binary to b.c.d. converter to determine whether any carries exist, a CAS flip-flop being provided to store resulting carries for addition to the next digit, the sum being returned to the memory. Memory.-The memory comprises a set of cores (Fig. 6) forming four registers each holding 16 four-bit words, one word being formed by the four black cores shown. Each register is determined by a bit XG 1 applied to an X decoder and a bit XG 2 applied to a Y decoder. The two least significant bits of the R or #R or T registers are applied to the X decoder and the two most significant bits to the Y decoder. Each decoder produces a signal on one out of 8 lines X 0 -X 7 , Y 0 -Y 7 to enable four cores for the reading and writing of a word. An inhibit signal DG determines the nature of data read into a core. Whenever any of the signals DG 1,2,4,8 is "1" a "0" is written into the appropriate enabled core, otherwise a "1" is written. Log generator.-The log generator comprises a diode matrix fixed memory containing the natural logs of a set of twelve constants, half the natural logs of the same set and twice the natural logs of the same set. The contents of the T register determine which of the constants is to be used and the R register determines which digit. Display unit.-The display unit comprises 10 digit display tubes plus a sign indicator tube. Each tube has ten cathodes, corresponding cathodes in each tube being coupled together. Only one tube anode is energized at any one time as determined by the contents of the T register. Each digit is sequentially transferred, under the control of the T register from the W register to the E register, which controls the cathode selection. Flow charts are given indicating the operations performed by the computer under control of counters. The computer operates in a series of b modes determined by a b counter producing ten major b modes. Signals applied by the counter to AND gates (Figs. 18-22, not shown) producing control signals depending on the state of the computer.
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公开(公告)号：US3474437A
公开(公告)日：1969-10-21
申请号：US3474437D
申请日：1966-06-15
Applicant: WANG LABORATORIES
Inventor： WANG AN
CPC classification number: G09G3/10 , G06F3/02 , G06F3/1407
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公开(公告)号：US3594734A
公开(公告)日：1971-07-20
申请号：US3594734D
申请日：1969-03-21
Applicant: WANG LABORATORIES
Inventor： WANG AN , ROBINSON PRENTICE I
Abstract: An electronic calculator system includes a keyboard unit having keys representing numerical values from 0 through 9 and additional keys representing instruction values. Logic responsive to key operation produces codes for numerical values and instruction values; these codes function to determine operations performed by the calculator. The system further includes a magnetic tape unit operable in either of two modes: a learn mode in which key actuation causes the codes to be recorded in predetermined sequence upon a loop of magnetic tape, and a normal mode in which the tape unit senses the codes upon the tape and produces signals responsive to the codes to control calculator operation.
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公开(公告)号：US3573746A
公开(公告)日：1971-04-06
申请号：US3573746D
申请日：1968-12-09
Applicant: WANG LABORATORIES
Inventor： ROBINSON PRENTICE I , CHANG NED , WANG AN
CPC classification number: G06F15/00
Abstract: An electronic calculator system includes an arithmetic unit, an input register that receives signals from a keyboard and optionally from one or more card readers for transmission to the arithmetic unit and a memory unit. The card readers are pluggably connected in series and each includes interlock control which cooperates with a program counter to channel instruction and numerical data to the arithmetic unit from the card reader through the input register. The memory unit includes two reversible address counters which in conjunction with a program stored in a card reader enable efficient performance of mathematical manipulations of the matrix type.
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公开(公告)号：US3428950A
公开(公告)日：1969-02-18
申请号：US3428950D
申请日：1966-03-22
Applicant: WANG LABORATORIES
Inventor： CHANG NED , ROBINSON PRENTICE I , WANG AN
Abstract: 1,160,612. Digital electric calculator. WANG LABORATORIES Inc. 13 March, 1967 [22 March, 1966 (2)], No. 11563/67. Heading G4A. A digital electric calculator apparatus comprises an arithmetic unit and first instruction supplying means including a plurality of manually operable keys and a second instruction supplying means including a record receiving device for receiving a record having data instructions encoded thereon in matrix fashion, a matrix of instruction sensors arranged in a series of groups, a plurality of sensor group actuators and a plurality of output lines, and first counting means to sequentially operate the sensor group actuators to provide instruction signals on the output lines. The calculator performs multiplication by forming the logarithm of a number, operating on the logarithm and producing an antilogarithm. A small store 166 contains the log. values of number 10,2,0À9,1À01, 0À999, 1À0001, the log. of a number entered in a work register 14 under the control of numeral keys 18 or a card reader 42 being formed by (a) sensing the position of a decimal point in register 22 and shifting the position to move it to the most significant stage and adding the value of log 10 to a zero value in a log register 28. (b) interrogating the most significant digit in register 14 to cause successive doubling of the number if the digit is a " 0 " or passing the number in register 14 through a delay circuit to divide by 10 and then subtracting from the original number to effectively multiply by 0À9 the two sequences causing log 2 to be subtracted from, and log 0À9 to be added to, the log register respectively. (c) when the most significant digit changes a " 1 " causes multiplication by 0À999 and a "0" causes multiplication by 1À0001 the appropriate logs being added or subtracted in the log. register. Card reader: read only memory.-Each card contains a matrix of prescored locations each of which may be removed by an operator to determine the appropriate instruction, each of 40 columns containing two six-bit words. The cards are placed in a card reader 42 (Fig. 2) having a base 69 carrying matrix 88 of kidneyshaped flat contacts and a cover 66 having pins 92 protruding through a matrix of holes in locations corresponding to the contacts of the base and the locations in the card. When any word is to be read the appropriate 6 bit column of the matrix 88 is energized. The punched locations in that column allow the signal to appear on pins 92. All the pins in each row are connected in series and to a corresponding set of pins in a further column 90 outside the area of the card. The energized pins in column 90 then energize contacts 86 in a column on the base 64 connected to a diode matrix to decode the signals. Two counters PC 30, DC 32 control the operation of reading the cards and performing the calculations. Program Counter 30 determines which column is read, and is normally incremented by 1 but may be jumped to provide a branching instruction. Decrement Counter 32 is normally decreased and used to determine the number of iterations that may be performed. A simple program read by the counters is described. The calculations are performed in serial fashion each bit being read into and combined in Adder Subtractors 110, 124, 162.
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