3. A LOGIC DECISION CIRCUIT COMPRISING A FIRST AND A SECOND AND GATE EACH HAVING AN INPUT FOR RECEIVING PULSES, AN OUTPUT TERMINAL AND AN ENABLING MEANS FOR PASSING THE INPUT PULSES TO THE OUTPUT TERMINAL DURING A FIRST AND SECOND PERIOD OF TIME RESPECTIVELY, A FIRST AND A SECOND RESETTABLE DIVIDE-BY-TWO CIRCUIT EACH HAVING AN INPUT TERMINAL CONNECTED TO A DIFFERENT ONE OF THE SAID FIRST AND SECOND AND GATES FOR RECEIVING THE PASSED PULSES, AN OUTPUT TERMINAL FOR PASSING EVERY SECOND RECEIVED PULSE, AND A RESET TERMINAL FOR SETTING THE FIRST AND SECOND DIVIDE-BY-TWO CIRCUITS IN AN INITIAL CONDITION FOR PASSING EVERY SECOND PULSE RECEIVED, A MULTI-STAGE RESETTABLE DECISION COUNTER MEANS CONNECTED TO BOTH OF SAID FIRST AND SECOND DIVIDE-BY-TWO CIRCUITS FOR COUNTING ALL PULSES PASSED BY SAID LAST-NAMED CIRCUITS AND PRODUCING AN OUTPUT PULSE WHENEVER THE SUM OF PULSES RECEIVED BY BOTH OF SAID FIRST AND SECOND DIVIDE-BY-TWO CIRCUITS IS GREATER THAN TWICE THE COUNTING CAPACITY OF THE DECISION COUNTER, AND PRODUCING NO OUTPUT PULSE WHENEVER THE TOTAL SUM OF PULSES RECEIVED BY SAID FIRST AND SECOND DI-

VIDE-BY-TWO CIRCUITS IS LESS THAN TWICE THE COUNTING CAPACITY OF DECISION COUNTER, AND PRODUCING AN OUTPUT PULSE WHENEVER THE SUM OF PULSES RECEIVED BY SAID FIRST AND SECOND DIVIDE-BY-TWO CIRCUITS IS EQUAL TO TWICE THE COUNTING CAPACITY OF THE COUNTER MEANS AND OBTAINED BY SUMMING AN EVEN NUMBER OF PULSES TO SAID FIRST DIVIDE-BYTWO CIRCUIT AND AN EVEN NUMBER OF PULSES TO SAID SECOND DIVIDE-BY-TWO CIRCUIT, AND PRODUCING NO OUTPUT PULSE WHENEVER THE SUM OF PULSES RECEIVED BY SAID FIRST AND SECOND DIVIDE-BY-TWO CIRCUITS IS EQUAL TO TWICE THE COUNTING CAPACITY OF THE COUNTER MEANS AND OBTAINED BY SUMMING AND OFF NUMBER OF PULSES TO SAID FIRST DIVIDE-BY-TWO CIRCUIT AND AN ODD NUMBER OF PULSES TO SAID SECOND DIVIDE-BY-TWO CIRCUIT, AND RESET MEANS FOR SETTING SAID, FIRST AND SECOND DIVIDE-BY-TWO CIRCUITS AND SAID DECISION COUNTER IN AN INITIAL CONDITION AT THE BEGINNING OF A CYCLE OF OPERATION.