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公开(公告)号：US4205396A
公开(公告)日：1980-05-27
申请号：US56529175
申请日：1975-03-25
申请人： US NAVY
发明人： PRYOR CABELL N JR
CPC分类号： G01S3/8036 , Y10S367/901
摘要： An automatic method for forming a generalized cardioid pattern from the three hydrophone signals of the DIFAR system to remove bearing bias and produce a minimum noise signal channel to substitute for the omnidirectional signal as a reference.
摘要翻译： 一种用于从DIFAR系统的三个水听器信号形成广义心形图案的自动方法，以移除轴承偏置并产生最小噪声信号通道以代替全向信号作为参考。
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公开(公告)号：US3564596A
公开(公告)日：1971-02-16
申请号：US3564596D
申请日：1962-06-29
申请人： US NAVY
发明人： PRYOR CABELL N JR
摘要： 3. A LOGIC DECISION CIRCUIT COMPRISING A FIRST AND A SECOND AND GATE EACH HAVING AN INPUT FOR RECEIVING PULSES, AN OUTPUT TERMINAL AND AN ENABLING MEANS FOR PASSING THE INPUT PULSES TO THE OUTPUT TERMINAL DURING A FIRST AND SECOND PERIOD OF TIME RESPECTIVELY, A FIRST AND A SECOND RESETTABLE DIVIDE-BY-TWO CIRCUIT EACH HAVING AN INPUT TERMINAL CONNECTED TO A DIFFERENT ONE OF THE SAID FIRST AND SECOND AND GATES FOR RECEIVING THE PASSED PULSES, AN OUTPUT TERMINAL FOR PASSING EVERY SECOND RECEIVED PULSE, AND A RESET TERMINAL FOR SETTING THE FIRST AND SECOND DIVIDE-BY-TWO CIRCUITS IN AN INITIAL CONDITION FOR PASSING EVERY SECOND PULSE RECEIVED, A MULTI-STAGE RESETTABLE DECISION COUNTER MEANS CONNECTED TO BOTH OF SAID FIRST AND SECOND DIVIDE-BY-TWO CIRCUITS FOR COUNTING ALL PULSES PASSED BY SAID LAST-NAMED CIRCUITS AND PRODUCING AN OUTPUT PULSE WHENEVER THE SUM OF PULSES RECEIVED BY BOTH OF SAID FIRST AND SECOND DIVIDE-BY-TWO CIRCUITS IS GREATER THAN TWICE THE COUNTING CAPACITY OF THE DECISION COUNTER, AND PRODUCING NO OUTPUT PULSE WHENEVER THE TOTAL SUM OF PULSES RECEIVED BY SAID FIRST AND SECOND DI-
VIDE-BY-TWO CIRCUITS IS LESS THAN TWICE THE COUNTING CAPACITY OF DECISION COUNTER, AND PRODUCING AN OUTPUT PULSE WHENEVER THE SUM OF PULSES RECEIVED BY SAID FIRST AND SECOND DIVIDE-BY-TWO CIRCUITS IS EQUAL TO TWICE THE COUNTING CAPACITY OF THE COUNTER MEANS AND OBTAINED BY SUMMING AN EVEN NUMBER OF PULSES TO SAID FIRST DIVIDE-BYTWO CIRCUIT AND AN EVEN NUMBER OF PULSES TO SAID SECOND DIVIDE-BY-TWO CIRCUIT, AND PRODUCING NO OUTPUT PULSE WHENEVER THE SUM OF PULSES RECEIVED BY SAID FIRST AND SECOND DIVIDE-BY-TWO CIRCUITS IS EQUAL TO TWICE THE COUNTING CAPACITY OF THE COUNTER MEANS AND OBTAINED BY SUMMING AND OFF NUMBER OF PULSES TO SAID FIRST DIVIDE-BY-TWO CIRCUIT AND AN ODD NUMBER OF PULSES TO SAID SECOND DIVIDE-BY-TWO CIRCUIT, AND RESET MEANS FOR SETTING SAID, FIRST AND SECOND DIVIDE-BY-TWO CIRCUITS AND SAID DECISION COUNTER IN AN INITIAL CONDITION AT THE BEGINNING OF A CYCLE OF OPERATION.-
公开(公告)号：US3660647A
公开(公告)日：1972-05-02
申请号：US3660647D
申请日：1969-12-24
申请人： US NAVY
发明人： PRYOR CABELL N JR
CPC分类号： G01S13/66 , G06G7/1921 , G06G7/1935
摘要： A system for varying the relative time delay between two broadband input signals consisting of an adjustable time delay coupled to one of two input channels of a two point clipper correlator. The correlator includes a plurality of cross-coupled exclusive OR gates which generate output signals only when the correlation functions of both channels correspond. Decisions made in the correlator at each sample time are used to vary the adjustable delay, to provide automatic tracking of the peak of the cross-correlation function between the input signals.
摘要翻译： 用于改变两个宽带输入信号之间的相对时间延迟的系统，该两个宽带输入信号由耦合到两点切换器相关器的两个输入通道之一的可调节时间延迟组成。 相关器包括多个交叉耦合异或门，仅在两个通道的相关函数对应时才产生输出信号。 在每个采样时间在相关器中进行的判定用于改变可调延迟，以提供对输入信号之间的互相关函数的峰值的自动跟踪。
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公开(公告)号：US3646333A
公开(公告)日：1972-02-29
申请号：US3646333D
申请日：1969-12-12
申请人： US NAVY
发明人： PRYOR CABELL N JR
CPC分类号： G06F17/15
摘要： A digital correlator and integrator which uses a core memory to implement the cross-correlation and post-integration operations simultaneously. The system is a hybrid correlator that treats one of two sample channels linearly while it delays and stores the information in the other channel. The samples from both channels are multiplied together then averaged repetitively into stored data to generate a time-compressed correlation function which is retained in digital form within the memory.
摘要翻译： 数字相关器和积分器，其使用核心存储器来同时实现互相关和后整合操作。 该系统是混合相关器，其在线性地处理两个采样通道中的一个，同时延迟并将信息存储在另一通道中。 将来自两个通道的样本相乘，然后重复平均地存储到存储的数据中，以产生以数字形式保存在存储器内的时间压缩相关函数。
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