Invention Grant
- Patent Title: Binary full adder utilizing operational amplifiers
- Patent Title (中): 二进制充分利用运算放大器
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Application No.: US3586845DApplication Date: 1967-09-06
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Publication No.: US3586845APublication Date: 1971-06-22
- Inventor: KOMAMIYA YASUO , KUROKAWA KAZUO , GOTO TATSUO , MORI RYOICHI , TAJIMA HIRAOKI
- Applicant: AGENCY IND SCIENCE TECHN
- Assignee: Agency Ind Science Techn
- Current Assignee: Agency Ind Science Techn
- Priority: JP6014966 1966-09-13
- Main IPC: G06F7/50
- IPC: G06F7/50 ; G06F7/501 ; G06F7/385
Abstract:
This invention relates to a digital logic circuit which incorporates an analogue operational amplifier as a component of the circuit.
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