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公开(公告)号：US12164882B2
公开(公告)日：2024-12-10
申请号：US17203130
申请日：2021-03-16
Inventor： Yu-Der Chih , Hidehiro Fujiwara , Yi-Chun Shih , Po-Hao Lee , Yen-Huei Chen , Chia-Fu Lee , Jonathan Tsung-Yung Chang
IPC: G06F7/501 , G06F7/53 , G11C7/10 , G11C11/4074
Abstract: A memory circuit includes a selection circuit, a column of memory cells, and an adder tree. The selection circuit is configured to receive input data elements, each input data element including a number of bits equal to H, and output a selected set of kth bits of the H bits of the input data elements. Each memory cell of the column of memory cells includes a first storage unit configured to store a first weight data element and a first multiplier configured to generate a first product data element based on the first weight data element and a first kth bit of the selected set of kth bits. The adder tree is configured to generate a summation data element based on each of the first product data elements.
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公开(公告)号：US12164375B2
公开(公告)日：2024-12-10
申请号：US17949655
申请日：2022-09-21
Applicant: Micron Technology, Inc.
Inventor： Leon Zlotnik , Eyal En Gad , Fan Zhou
IPC: G06F11/10 , G06F7/501 , G06F11/07 , G11C29/44 , G11C29/52 , H03M13/11 , H03M13/15 , H03M13/29 , H03M13/37 , H03M13/45
Abstract: A method includes determining a quantity of errors for a bit string based on a quantity of bits having a logical value of one within the bit string and writing an indication corresponding to the quantity of errors for the bit string to an array of memory cells. The method can further include determining that the quantity of errors for the bit string has reached a threshold quantity of errors and refraining from performing a subsequent operation to determine the quantity of errors for the bit string in response to determining that the quantity of errors for the bit string has reached the threshold quantity of errors.
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公开(公告)号：US12141657B2
公开(公告)日：2024-11-12
申请号：US18309486
申请日：2023-04-28
Applicant: University of Maryland, College Park , IonQ, Inc.
Inventor： Caroline Figgatt , Aaron Ostrander , Norbert M. Linke , Kevin A. Landsman , Daiwei Zhu , Dmitri Maslov , Christopher Monroe
Abstract: The disclosure describes various aspects related to enabling effective multi-qubit operations, and more specifically, to techniques for enabling parallel multi-qubit operations on a universal ion trap quantum computer. In an aspect, a method of performing quantum operations in an ion trap quantum computer or trapped-ion quantum system includes implementing at least two parallel gates of a quantum circuit, each of the at least two parallel gates is a multi-qubit gate, each of the at least two parallel gates is implemented using a different set of ions of a plurality of ions in a ion trap, and the plurality of ions includes four or more ions. The method further includes simultaneously performing operations on the at least two parallel gates as part of the quantum operations. A trapped-ion quantum system and a computer-readable storage medium corresponding to the method described above are also disclosed.
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4.发明公开
公开(公告)号：US20240345805A1
公开(公告)日：2024-10-17
申请号：US18753107
申请日：2024-06-25
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Pankaj GUPTA , Karthik SUBBURAJ , Sujaata RAMALINGAM , Karthik RAMASUBRAMANIAN , Indu PRATHAPAN
CPC classification number: G06F7/49 , G06F7/501 , G06F17/142
Abstract: A system includes Radix-22 butterfly stages, each including first and second Radix-22 butterfly circuits, in which the first Radix-22 butterfly circuit of a first Radix-22 butterfly stage includes a data input coupled to a system data input, and one of the first Radix-22 butterfly circuit and the second Radix-22 butterfly circuit of a last Radix-22 butterfly stage includes a data output coupled to a system data output. The system further includes a Radix-3 butterfly circuit including a data input coupled to the system data input and a data output selectively couplable to a data input of one of the first or second Radix-22 butterfly circuits of a second or later Radix-22 butterfly stage based on a particular point transform to be performed by the system. A set of memories are used by either the first Radix-22 butterfly stage or the Radix-3 butterfly circuit, depending on the particular point transform.
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公开(公告)号：US12106822B2
公开(公告)日：2024-10-01
申请号：US17852193
申请日：2022-06-28
Applicant: MEDIATEK Singapore Pte. Ltd.
Inventor： Chetan Deshpande , Gajanan Sahebrao Jedhe , Gaurang Prabhakar Narvekar , Cheng-Xin Xue , Sushil Kumar , Zijie Guo
CPC classification number: G11C7/1069 , G06F7/501 , G06F7/5443 , G11C7/1012 , G11C7/1096 , G11C7/12 , G11C8/06 , G11C8/08
Abstract: Aspects of the present disclosure are directed to devices and methods for performing MAC operations using a memory array as a compute-in-memory (CIM) device that can enable higher computational throughput, higher performance and lower energy consumption compared to computation using a processor outside of a memory array. In some embodiments, an activation architecture is provided using a bit cell array arranged in rows and columns to store charges that represent a weight value in a weight matrix. A read word line (RWL) may be repurposed to provide the input activation value to bit cells within a row of bit cells, while a read-bit line (RBL) is configured to receive multiplication products from bit cells arranged in a column. Some embodiments provide multiple sub-arrays or tiles of bit cell arrays.
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6.发明授权
公开(公告)号：US12075179B2
公开(公告)日：2024-08-27
申请号：US18047588
申请日：2022-10-18
Applicant: OMNIVISION TECHNOLOGIES, INC.
Inventor： Rui Wang
IPC: H04N25/772 , G06F7/501 , G06F7/57
CPC classification number: H04N25/772 , G06F7/501 , G06F7/57
Abstract: An arithmetic logic unit (ALU) includes a front end latch stage coupled to a signal latch stage coupled to a Gray code (GC) to binary stage. First inputs of an adder stage are coupled to receive outputs of the GC to binary stage. An adder input latch stage includes first and second adder input latches including first and second inputs coupled to receive outputs of the GC to binary stage. An adder input multiplexer stage includes an output coupled to second inputs of the adder stage, and first and second inputs coupled to outputs the first and second adder input latches, respectively.
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7.发明授权
公开(公告)号：US12045582B2
公开(公告)日：2024-07-23
申请号：US17351699
申请日：2021-06-18
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Pankaj Gupta , Karthik Subburaj , Sujaata Ramalingam , Karthik Ramasubramanian , Indu Prathapan
CPC classification number: G06F7/49 , G06F7/501 , G06F17/142
Abstract: A Radix-3 butterfly circuit includes a first FIFO input configured to couple to a first FIFO. The circuit includes a first adder and first subtractor coupled to the first FIFO input, and a second FIFO input configured to couple to a second FIFO. The circuit includes a second adder and second subtractor coupled to the second FIFO input, and an input terminal coupled to the first adder and first subtractor. The circuit includes a first scaler coupled to the second adder and a first multiplexer, and a second scaler coupled to a third adder and second multiplexer. The circuit includes a third scaler coupled to a third subtractor and third multiplexer. An output of the first multiplexer is coupled to a complex multiplier. An output of the second multiplexer is coupled to a second FIFO output. An output of the third multiplexer is coupled to a first FIFO output.
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公开(公告)号：US20240126507A1
公开(公告)日：2024-04-18
申请号：US18544313
申请日：2023-12-18
Applicant: Imagination Technologies Limited
Inventor： Sam Elliott , Jonas Olof Gunnar KALLEN , Casper Van Benthem
Abstract: Adder circuits and associated methods for processing a set of at least three floating-point numbers to be added together include identifying, from among the at least three numbers, at least two numbers that have the same sign—that is, at least two numbers that are both positive or both negative. The identified at least two numbers are added together using one or more same-sign floating-point adders. A same-sign floating-point adder comprises circuitry configured to add together floating-point numbers having the same sign and does not include circuitry configured to add together numbers having different signs.
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公开(公告)号：US20240112003A1
公开(公告)日：2024-04-04
申请号：US18077993
申请日：2022-12-08
Applicant: Silicon Storage Technology, Inc.
Inventor： HIEU VAN TRAN , STEPHEN TRINH , STANLEY HONG , THUAN VU , NGHIA LE , HIEN PHAM
Abstract: Numerous examples are disclosed of output circuitry and associated methods in an artificial neural network. In one example, a system comprises an array of non-volatile memory cells arranged into rows and columns, an output block to convert current from columns of the array into a first digital output during a first time period and a second digital output during a second time period, a first output register to store the first digital output during the first time period and to output the stored first digital output during the second time period, and a second output register to store the second digital output during the second time period and to output the stored second digital output during a third time period.
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公开(公告)号：US20240094987A1
公开(公告)日：2024-03-21
申请号：US18329856
申请日：2023-06-06
Applicant: Samsung Electronics Co., Ltd.
Inventor： Byoung Gon Kang
IPC: G06F7/501 , G06F30/392 , H01L27/118 , H03K17/00 , H03K19/21
CPC classification number: G06F7/501 , G06F30/392 , H01L27/11807 , H03K17/002 , H03K19/21 , H01L2027/11881 , H01L2027/11885
Abstract: A compressor circuit and a semiconductor integrated circuit included the compressor circuit are provided. The semiconductor integrated circuit includes a compressor circuit which includes a first full adder circuit which receives an A1 signal, a B1 signal, and a CI signal to output an IS signal and an ICO signal, and a second full adder circuit which receives a B2 signal, the IS signal, and a CI2 signal to output an S signal and a CO signal. Each of the first full adder circuit and the second full adder circuit are in an L-shaped layout, the first full adder circuit and the second full adder circuit have bent portions that are point-symmetrically engaged with each other, and the compressor circuit is in a rectangular shape. The number of transistors in the second full adder circuit is smaller than the number of transistors in the first full adder circuit.
