发明授权
- 专利标题: Two{40 s complement negative number multiplying circuit
- 专利标题(中): 两个{40 S补充负数乘法电路
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申请号: US3627999D申请日: 1969-11-28
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公开(公告)号: US3627999A公开(公告)日: 1971-12-14
- 发明人: IVERSON GARY J
- 申请人: COMCET INC
- 专利权人: Comcet Inc
- 当前专利权人: Comcet Inc
- 优先权: US88065369 1969-11-28
- 主分类号: G06F7/52
- IPC分类号: G06F7/52 ; G06F7/38 ; G06F7/39
摘要:
A two''s complement negative number multiplying circuit in which no complementing of the multiplier or multiplicand is required, no special cases need be detected, no complementing of the result is required and fewer transfer paths are needed.