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58 条记录 (耗时 0.012 秒)

    Multiple-generating register
    1.
    发明授权
    Multiple-generating register 失效
    多生成寄存器

    公开(公告)号：US3949209A

    公开(公告)日：1976-04-06

    申请号：US565182

    申请日：1975-04-04

    申请人： Darrell L. Fett

    发明人： Darrell L. Fett

    IPC分类号： G06F7/508 ,  G06F7/52 ,  G06F7/523 ,  G06F7/53 ,  G06F7/533 ,  G06F7/39

    CPC分类号： G06F7/5338 ,  G06F2207/4806

    摘要： A multiple-generating register generates one of several possible multiples of a binary number which is input thereto in response to a respective one of a plurality of multiple-generating commands. The multiple-generating register comprises a control circuit for generating the multiple-generating commands in response to a three-bit control signal and comprises further a plurality of selector latch logic circuits. Each selector latch logic circuit receives as a first input a respective bit of the input binary number and receives as a second input the next lowest order bit of the input binary number, except that the selector latch logic circuit which receives as a first input the lowest order bit of the input binary number receives as a second input a zero-valued binary bit. The plurality of selector latch logic circuits generate a binary number that is a multiple of the input binary number, which multiple is equal to the input binary number times .+-.1, .+-.2, or 0, depending upon the informational content of the three-bit control signal.

    摘要翻译： 多生成寄存器响应于多个多生成命令中的相应一个生成二进制数的多个可能的倍数而被输入到其中。 多产生寄存器包括用于响应于三位控制信号产生多个生成命令的控制电路，并且还包括多个选择器锁存逻辑电路。 每个选择器锁存逻辑电路作为第一输入接收输入二进制数的相应位，并且作为第二输入接收输入二进制数的下一个最低位，除了作为第一输入接收的选择器锁存逻辑电路最低 输入二进制数的顺序位作为第二输入接收零值二进制位。 多个选择器锁存逻辑电路产生作为输入二进制数的倍数的二进制数，其中多个等于输入二进制数乘以+/- 1，+/- 2或0，这取决于信号内容 三位控制信号。

    Apparatus and method for serial-parallel binary multiplication
    3.
    发明授权
    Apparatus and method for serial-parallel binary multiplication 失效
    用于串并行二进制多路复用的装置和方法

    公开(公告)号：US3816732A

    公开(公告)日：1974-06-11

    申请号：US34610873

    申请日：1973-03-29

    申请人： ROCKLAND SYSTEMS CORP

    发明人： JACKSON L

    IPC分类号： G06F7/52 ,  G06F7/39

    CPC分类号： G06F7/5272 ,  G06F7/49947

    摘要： The bits of the multiplier are multiplied by sequential bits of the multiplicand in ascending order of significance. These sequential products are supplied to a parallel adder, where each bit is added to the delayed sum of the preceding operation of the next higher bit in order of significance, including the carry bit as the most significant. After k bits of multiplicand have been used, truncated or rounded output becomes available at the output of the least significant stage of the adder. During the bit interval of the last bit of the multiplicand the outputs of the adder are loaded into a parallel input series output shift register, after which the remaining bits of the product are taken from the output of the shift register, the delayed flipflops associated with the adder are cleared and the adder begins to operate on the next multiplication while the shift register is unloading.

    摘要翻译： 乘法器的位以有效数字的升序乘以被乘数的顺序位。 这些顺序产品被提供给并行加法器，其中每个比特按照重要性的顺序被加到下一较高比特的前一个操作的延迟和，包括进位比特最高。 在使用被乘数的k位之后，截断或舍入的输出在加法器的最低有效级的输出端可用。 在被乘数的最后一位的比特间隔期间，加法器的输出被加载到并行输入串行输出移位寄存器中，之后产品的剩余位取自移位寄存器的输出，延迟的触发器与 当移位寄存器卸载时，加法器被清零，加法器开始在下一个乘法运算。

    Machine processing of algebraic information
    7.
    发明授权
    Machine processing of algebraic information 失效
    代数信息的机器处理

    公开(公告)号：US3614406A

    公开(公告)日：1971-10-19

    申请号：US3614406D

    申请日：1964-09-30

    申请人： BELL TELEPHONE LABOR INC

    发明人： BROWN WILLIAM S

    IPC分类号： G06F7/544 ,  G06F7/385 ,  G06F7/00 ,  G06F7/39

    CPC分类号： G06F7/544

    摘要： A method and apparatus are disclosed for improving the efficiency of processing and storing algebraic and similar information in a data processor. Polynomial information is treated as an array of coefficient and exponent information subject to machine boundary conditions, user format statements and linking signals. Dynamic storage allocation and exponent overflow are also provided.

    Automatic electronic counter apparatus
    8.
    发明授权
    Automatic electronic counter apparatus 失效
    自动电子计数器

    公开(公告)号：US3555256A

    公开(公告)日：1971-01-12

    申请号：US3555256D

    申请日：1968-07-26

    申请人： GEN RADIO CO

    发明人： WESTLAKE NORMAN L

    IPC分类号： G01R23/10 ,  G06F7/38 ,  G06F7/39

    CPC分类号： G01R23/10

    摘要： An improved automatic electronic digital counter is disclosed in which frequency-range switching is automatically effected and a quotient of the count of a clock pulse-fed counting register and a signal-period counting register is continually indicated.

    Integrated arithmetic unit and digital networks using the unit
    10.
    发明授权
    Integrated arithmetic unit and digital networks using the unit 失效
    集成运算单元和使用该单元的数字网络

    公开(公告)号：US4128890A

    公开(公告)日：1978-12-05

    申请号：US811194

    申请日：1977-06-29

    申请人： John M. Irwin ,  Fritz H. Schlereth

    发明人： John M. Irwin ,  Fritz H. Schlereth

    IPC分类号： G06F7/52 ,  G06F7/544 ,  G06F17/15 ,  G06F15/34 ,  G06F7/39

    CPC分类号： G06F17/15 ,  G06F7/525 ,  G06F7/544 ,  G06F2207/3816 ,  G06F7/49947 ,  G06F7/49994

    摘要： The invention relates to an arithmetic unit fabricated by large scale integration techniques and to an improved digital network of increased accuracy in which the unit finds application. The integrated circuit comprises an initial summing means, rounding means, full precision multiplication logic and three successive summing means, all elements being successively connected, and all except the first having both internal and external input terminals. The unit is flexible in respect to the length of the operands and their sign notation. The terminals are readily cascaded, permitting interconnection of the unit with like integrated circuit units and with external delay elements. The invention is applicable in a variety of complex operations including digital filtering, correlation, convolution, polynomial evaluation and squaring. In many of these applications, mixed precision and rounding provide increased accuracy in the resulting digital networks.

    摘要翻译： 本发明涉及一种通过大规模集成技术制造的算术单元和一种改进的数字网络，其中单元可以获得应用。 集成电路包括初始求和装置，舍入装置，全精度乘法逻辑和三个连续求和装置，所有元件被连续连接，除了第一个具有内部和外部输入端之外的所有元件。 该单元在操作数的长度和符号符号方面是灵活的。 端子容易级联，允许单元与类似的集成电路单元和外部延迟元件的互连。 本发明适用于数字滤波，相关，卷积，多项式评估和平方的各种复杂操作。 在许多这些应用中，混合精度和舍入在所得数字网络中提供更高的精度。