A serial-parallel two''s complement binary multiplier circuit featuring a tightly clocked arrangement facilitating the formation of a product signal in an interval of duration shorter than the arrival interval for a serial multiplicand word. Hence, the multiplier circuit is capable of processing butted-word inputs in real time with only minor constraints on word formats. The multiplication algorithm features a pairwise summation of partial products on a least-significant-bit-first basis which gives rise to a tree-like structure of substantially identical circuit modules. Negative multiplicands are treated using a postmultiplication correction circuit.