Apparatus for digital frequency multiplication having a first AND logic gate adapted to receive an input pulse train having a frequency fin, each pulse width defining one iteration. A numerator shift register with digital contents N, is connected to the input of the first AND logic gate, the latter gate, when enabled by the signal fin, having the digital output N. A denominator shift register, having digital contents D is connected to the input of a second AND logic gate. An accumulator register coupled to the outputs of both AND gates, having digital contents R, is applied to a comparator, which compares the contents R with a datum level. The comparator delivers an output signal fo when R