A pulse counter including AND, OR, NOT gates and their combinations comprises two n-stage flip-flops, where n 5, 6, ..... , the outputs of the first one of these flip-flops being connected through a first group of n AND gates to the inputs of the other flip-flop, the outputs of the latter being connected through a second group of n AND gates to the inputs of the first flip-flop. The other inputs of the AND gates in each group are interconnected and form the respective count inputs of the counter. In the n-stage flip-flops of the counter the output of each one of the n stages is connected to the inputs of s other inputs of the same flip-flop, and each one of the inputs of each said flip-flop is connected to the inputs of s stages of the same flip-flop, where 2 > OR = s > OR = n-3.