A dead-zone comparator includes first and second voltage comparators used respectively to compare an input signal to a high reference level and to a low reference level, which reference levels can be programmed. A bistable memory element is set by the output signal of one comparator and reset by the output signal of the other. These SET and RESET signals are opposite polarity currents, one of which is more severely constrained in value than the other, and are applied via a common SET-RESET buss to the memory element. When the memory element is in its SET condition, a relaxation oscillator is permitted to deliver output pulses of sufficient magnitude to trigger SCR''s or triacs directly. When the memory element is in its RESET condition, the relaxation oscillator is prevented from furnishing any output pulses.