发明授权
- 专利标题: Analog-to-digital converter utilizing time reference for effecting conversion
- 专利标题(中): 利用时间基准的模数转换器实现转换
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申请号: US527717申请日: 1974-11-27
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公开(公告)号: US3987435A公开(公告)日: 1976-10-19
- 发明人: Masayuki Ikeda
- 申请人: Masayuki Ikeda
- 申请人地址: JA Tokyo
- 专利权人: Kabushiki Kaisha Suwa Seikosha
- 当前专利权人: Kabushiki Kaisha Suwa Seikosha
- 当前专利权人地址: JA Tokyo
- 优先权: JA48-133185 19731128; JA48-137544 19731210
- 主分类号: G06J1/00
- IPC分类号: G06J1/00 ; H03M1/00 ; H03K13/02
摘要:
An analog-to-digital converter adapted to utilize a counting circuit including a quartz crystal vibrator time standard as the time reference for effecting analog-to-digital conversion. The converter includes oscillator means for producing a time standard signal, and counter means including a plurality of series-connected divider stages adapted to produce timing signals representative of the counts thereof in response to the time standard signal. Coincidence circuitry is coupled to a first plurality of the divider stages to produce a signal in response to the coincidence of the count of the first plurality of counters and a preselected count of the coincidence circuit. Control means produce first and second control signals in response to the coincidence signal from the coincidence circuit and the timing signals from the remaining divider stages in the counter circuit. Voltage supply circuitry is coupled to the control circuitry in order to apply an analog voltage in response to a first control signal, and in response to a second control signal from said control means, apply a reference voltage of a polarity opposite to the analog voltage to integrate the analog voltage applied thereto, and thereby effect an integration of the reference voltage of opposite polarity applied thereto, to thereby sum both voltages to zero. Digital processing circuitry is coupled to said integrator circuit and the first plurality of divider stages, and in response to detecting the integrator circuit summing to zero, processes to elapsed time required for the reference voltage to be summed to zero counted by the first plurality of divider stages, the elapsed time digitally representing the analog voltage applied to the integrator circuit.
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