发明授权
US4109102A Phase synchronizing circuit 失效
相位同步电路

Phase synchronizing circuit
摘要:
A phase synchronizing circuit for processing a 2.sup.n- phase phase modulated input signal wherein the signal is detected by phase detectors each of whose outputs are then phase shifted through a phase angle determined by the ratio of a:b = 1:tan (.pi./2.sup.n+1) where a represents the amplitude of the phase detector output and b represents the amplitude of a signal orthogonal to the signal a. The 2.sup.n phase shifted signals repetitively undergo frequency doubling and then a combined signal from each pair of doublers is generated to successively reduce the signals to 2.sup.n-1 in number, then 2.sup.n-2 in number, and so forth, until only one pair of signals remains. A difference signal of the pair of signals is formed, which difference signal represents an error signal and is employed to operate a voltage controlled oscillator serving as the signal to be compared at each phase detector with the input signal, after undergoing an appropriate phase shift.The phase shift of each phase detector output signal is accomplished by attenuating the output signal of that one of the remaining phase detectors which is orthogonal with the output signal undergoing phase shift wherein the respective ratios of the amplitudes of the signals are 1:tan (.pi./2.sup.n+1). The output signal being phase shifted and the attenuated output signal being used to control the magnitude of the phase shift are combined in an adder (or subtractor) circuit to effect the phase shift.
公开/授权文献
信息查询
0/0