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公开(公告)号：US4285062A
公开(公告)日：1981-08-18
申请号：US79725
申请日：1979-09-28
CPC分类号： H04L27/02 , H04L27/362 , H04L27/3872
摘要： A digital multi-level multi-phase modulation system utilizes quaternary differential encoding and decoding of only the first two of N digital signal trains. A decision circuit is used to examine the frame pulses in one of the first two signal trains and in at least one of the remaining signal trains and generates output signals which can be used in a gate circuit to resolve the phase-lock ambiguity of the recovered carrier and thereby reproduce the original N signal trains.
摘要翻译： 数字多电平多相调制系统仅使用N个数字信号序列中的前两个的四进制差分编码和解码。 使用判定电路来检查前两个信号列之一和剩余信号列中的至少一个中的帧脉冲，并且产生输出信号，其可以在门电路中使用以解决所恢复的相位锁定模糊度 从而再现原始的N信号列车。
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2.发明授权
公开(公告)号：US4525676A
公开(公告)日：1985-06-25
申请号：US351258
申请日：1982-02-22
申请人： Masaaki Atobe , Yoshimi Tagashira
发明人： Masaaki Atobe , Yoshimi Tagashira
IPC分类号： H04L27/227 , H03D3/02
CPC分类号： H04L27/2277
摘要： A system for demodulation of phase shift keying signals with a bandpass filter tracked to input carrier frequency variation. This system provides means for detecting phase variations in the regenerated carrier wave from the demodulated signal, and means for controlling the phase of the regenerated carrier wave to compensate for the demodulation error owing to input carrier frequency variation.
摘要翻译： 用带通滤波器解调相移键控信号的系统，用于输入载波频率变化。 该系统提供用于检测来自解调信号的再生载波中的相位变化的装置，以及用于控制再生载波的相位以补偿由于输入载波频率变化引起的解调误差的装置。
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公开(公告)号：US4110706A
公开(公告)日：1978-08-29
申请号：US730292
申请日：1976-10-06
IPC分类号： H04L27/227 , H03C3/00
CPC分类号： H04L27/2277
摘要： A synchronizing circuit for reproducing a synchronizing carrier wave from a received N-phase (N=2.sup.n, n being a positive real integer where n .gtoreq.1) PSK modulated carrier wave and employing a code converter circuit for adjusting the phase states of the received modulated carrier after demodulation thereof in order to enable the modulator to generate signals of the proper phase relation relative to an output carrier wave of a voltage controlled oscillator, which phase relationship is detected by a phase detector.The code converter may be a logic gating circuit having control inputs for changing the output levels or a plurality of branching circuit pairs for each input each pair having a true and complement branch, and switch means for selectively coupling one of the branches to an output associated with each pair of branch circuits.
摘要翻译： 一种同步电路，用于从接收的N相（N = 2n，n为正实数整数，其中n> / = 1）PSK调制载波再现同步载波，并采用代码转换器电路来调整相位状态 在解调之后接收调制载波，以使得调制器能够产生相对于压控振荡器的输出载波的适当相位关系的信号，该相位关系由相位检测器检测。
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公开(公告)号：US4109102A
公开(公告)日：1978-08-22
申请号：US743910
申请日：1976-11-22
IPC分类号： H04L27/227 , H04L7/00
CPC分类号： H04L27/2273
摘要： A phase synchronizing circuit for processing a 2.sup.n- phase phase modulated input signal wherein the signal is detected by phase detectors each of whose outputs are then phase shifted through a phase angle determined by the ratio of a:b = 1:tan (.pi./2.sup.n+1) where a represents the amplitude of the phase detector output and b represents the amplitude of a signal orthogonal to the signal a. The 2.sup.n phase shifted signals repetitively undergo frequency doubling and then a combined signal from each pair of doublers is generated to successively reduce the signals to 2.sup.n-1 in number, then 2.sup.n-2 in number, and so forth, until only one pair of signals remains. A difference signal of the pair of signals is formed, which difference signal represents an error signal and is employed to operate a voltage controlled oscillator serving as the signal to be compared at each phase detector with the input signal, after undergoing an appropriate phase shift.The phase shift of each phase detector output signal is accomplished by attenuating the output signal of that one of the remaining phase detectors which is orthogonal with the output signal undergoing phase shift wherein the respective ratios of the amplitudes of the signals are 1:tan (.pi./2.sup.n+1). The output signal being phase shifted and the attenuated output signal being used to control the magnitude of the phase shift are combined in an adder (or subtractor) circuit to effect the phase shift.
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公开(公告)号：US4338574A
公开(公告)日：1982-07-06
申请号：US134001
申请日：1980-03-26
CPC分类号： H03L7/087 , H03L7/113 , H04L27/2273 , H04L2027/0028 , H04L2027/0067
摘要： The voltage controlled oscillator (VCO) in a phase-locked loop carrier recovery circuit is provided with two control signals, one based upon a phase error between the phase modulated carrier and VCO output and the other based upon a frequency error between the phase modulated carrier and VCO output.
摘要翻译： 锁相环载波恢复电路中的压控振荡器（VCO）具有两个控制信号，一个基于相位调制载波和VCO输出之间的相位误差，另一个基于相位调制载波之间的频率误差 和VCO输出。
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6.发明授权
公开(公告)号：US4121166A
公开(公告)日：1978-10-17
申请号：US850518
申请日：1977-11-11
IPC分类号： H03L7/10 , H03L7/12 , H04L27/227 , H03D3/02
CPC分类号： H04L27/2272 , H03L7/10 , H03L7/12 , Y10S331/02
摘要： A phase synchronizing circuit for the demodulation of multi-phase PSK signals has a broadened capture frequency range while avoiding false capture. The circuit includes a phase synchronizing loop having a voltage controlled oscillator for generating a variable frequency output in response to a control voltage and a phase comparator for providing a comparison output representative of the phase difference between the output of the voltage controlled oscillator and an input signal. The comparison output serves as the control voltage for the voltage controlled oscillator. A phase-lock detection circuit is connected to the phase synchronizing loop to detect the phase-synchronized or unsynchronized states of the loop. A low frequency sweep generator is responsive to the phase-lock detection circuit for generating a variable-amplitude voltage which is supplied as a frequency sweep voltage to the voltage controlled oscillator. The frequency sweep voltage is provided for a period of time running from the detection by phase-lock detection circuit of the phase unsynchronized state to a predetermined period of time after the detection of the change from the phase unsynchronized state to the synchronized state.
摘要翻译： 用于解调多相PSK信号的相位同步电路具有扩大的捕获频率范围，同时避免错误捕获。 该电路包括一个相位同步回路，具有一个压控振荡器，用于响应一个控制电压产生一个可变频率输出;一个相位比较器，用于提供代表压控振荡器的输出与输入信号之间的相位差的比较输出 。 比较输出用作压控振荡器的控制电压。 相位锁定检测电路连接到相位同步环路，以检测环路的相位同步或非同步状态。 低频扫描发生器响应于锁相检测电路，用于产生作为频率扫描电压提供给压控振荡器的可变幅度电压。 在检测到从相位不同步状态到同步状态的变化之后，将频率扫描电压提供从从相位不同步状态的相位锁定检测电路的检测运行到预定时间段的时间段。
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7.发明授权Device for eliminating FM or like interference from a digital microwave signal 失效用于消除数字微波信号中的FM或类似干扰的装置
公开(公告)号：US4501004A
公开(公告)日：1985-02-19
申请号：US460961
申请日：1983-01-25
CPC分类号： H04B1/1036
摘要： In an interference elimination device for use in a digital microwave communication system in which an interference component results from at least one different microwave communication system sharing a frequency band in common, a controller (21) controls a device input signal so that a controlled signal thereby produced may include a controlled component which is equal in amplitude to the interference component and be antiphase relative thereto. The controlled signal is subtracted from the device input signal to provide a difference signal which is free from the interference component. Together with the device input signal, the difference signal is supplied to a control signal producing circuit (41) for producing an amplitude and a phase control signal for the controller. Instead of the device input signal, an interference signal derived by causing the device input signal to pass through a narrow-band filter (11 or 12) may be delivered to the controller and the control signal producing circuit. It is possible to use the difference signal as a device output signal and to implement the control signal producing circuit by an orthogonal multiplier.
摘要翻译： 在用于数字微波通信系统中的干扰消除装置中，控制器（21）控制装置输入信号，从而控制信号从而产生来自共同共同频带的至少一个不同的微波通信系统的干扰成分 所产生的可以包括与干涉分量相等幅度的受控分量，并且相对于其相反。 从设备输入信号中减去受控信号，以提供无干扰分量的差分信号。 与设备输入信号一起，差分信号被提供给用于产生控制器的幅度和相位控制信号的控制信号产生电路（41）。 代替设备输入信号，通过使器件输入信号通过窄带滤波器（11或12）导出的干扰信号可以传送到控制器和控制信号产生电路。 可以使用差分信号作为器件输出信号，并通过正交乘法器实现控制信号产生电路。
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公开(公告)号：US3967220A
公开(公告)日：1976-06-29
申请号：US600682
申请日：1975-07-31
摘要： A variable delay equalizer comprises two directional couplers, each having a pair of input terminals and a pair of output terminals. A pair of variable phase shifters are inserted respectively between the output terminals of the first coupler and the input terminals of the second coupler. A third variable phase shifter is connected between the second output terminal of the second coupler and the second input terminal of the first coupler. This equalizer makes it possible to shift the peak delay frequency as well as to change the value of the peak delay itself.
摘要翻译： 可变延迟均衡器包括两个定向耦合器，每个具有一对输入端子和一对输出端子。 一对可变移相器分别插入在第一耦合器的输出端和第二耦合器的输入端之间。 第三可变移相器连接在第二耦合器的第二输出端和第一耦合器的第二输入端之间。 该均衡器使得可以移位峰值延迟频率以及改变峰值延迟本身的值。
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