发明授权
- 专利标题: Apparatus for calculating a plurality of interpolation values
- 专利标题(中): 用于计算多个内插值的装置
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申请号: US967420申请日: 1978-12-07
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公开(公告)号: US4231097A公开(公告)日: 1980-10-28
- 发明人: Shigeki Shibayama , Kazuhide Iwata , Nobuo Okuda
- 申请人: Shigeki Shibayama , Kazuhide Iwata , Nobuo Okuda
- 申请人地址: JPX
- 专利权人: Tokyo Shibaura Denki Kabushiki Kaisha
- 当前专利权人: Tokyo Shibaura Denki Kabushiki Kaisha
- 当前专利权人地址: JPX
- 优先权: JPX52/148171 19771212
- 主分类号: G01N23/04
- IPC分类号: G01N23/04 ; A61B6/03 ; G06F17/17 ; G06T1/00 ; G06T11/00 ; G06F15/42
摘要:
Apparatus for calculating a plurality of interpolation values is adapted to calculate linear interpolation values, consisting of a second data train, from a first data train and includes a memory for storing the first data train and a calculator for calculating the interpolation value from the corresponding two data in the first data train read out of the memory. The calculator comprises an n-bit register for designating those addresses of the memory where data to be read out of the upper m-bit section of the n-bit register is stored and for determining weighted factor data for calculating the interpolation value at the lower (n-m) bit section of the register, a calculating unit for calculating the interpolation value from the data read out of the memory and the weighting coefficient data, an adder for adding a position increment value for designating the adjacent interpolation value to the register each time each interpolation value is calculated at the calculating unit, and a counter stepped one count for each calculation of each interpolation value and adapted to send an end signal to a central processing unit when a predetermined number of counts are completed. The memory, register, adder and counter are controlled by the central processing unit.
公开/授权文献
- US5944105A Well stabilization methods 公开/授权日:1999-08-31
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