A circuit for use in digital charge coupled systems provides successive indications of input binary value, until reset, without timing delays and without degeneration of the charge packets. A data input charge packet is provided to a storage electrode, and a series of standardized charge packets are also provided to the storage electrode at the data rate of the system. The latch circuit operates cyclically in internal cycles between the arrival of successive standardized charge packets. The concurrent presence of an input charge packet and a standardized charge packet results in charge overflow across a barrier in a first output data channel. This overflow causes a floating gate electrode that interconnects the first output channel with a second output channel to block transfer of the basic charge packet out the second output channel. It also causes the basic charge packet to be returned as a data input back to the storage electrode. With the basic charge packet representing a binary "1", therefore, the recirculation is effected with each arrival of a new standardized data packet. In the interim, however, the binary "1" valued charge packet is provided as an output at each clock interval from the first output channel. If the input represents binary "0", the floating gate does not inhibit transfer and a charge packet is not provided at the first output channel inasmuch as there is no overflow. Instead, an output charge packet is transferred out the second output channel to provide the complement of the data signal.