公开(公告)号：US4238693A

公开(公告)日：1980-12-09

申请号：US938952

申请日：1978-09-01

申请人： Reginald A. Allen

发明人： Reginald A. Allen

IPC分类号： G11C19/28 ,  H01L27/105 ,  H01L29/78 ,  H03K19/20

CPC分类号： G11C19/285 ,  H01L27/1057

摘要： A circuit for use in digital charge coupled systems provides successive indications of input binary value, until reset, without timing delays and without degeneration of the charge packets. A data input charge packet is provided to a storage electrode, and a series of standardized charge packets are also provided to the storage electrode at the data rate of the system. The latch circuit operates cyclically in internal cycles between the arrival of successive standardized charge packets. The concurrent presence of an input charge packet and a standardized charge packet results in charge overflow across a barrier in a first output data channel. This overflow causes a floating gate electrode that interconnects the first output channel with a second output channel to block transfer of the basic charge packet out the second output channel. It also causes the basic charge packet to be returned as a data input back to the storage electrode. With the basic charge packet representing a binary "1", therefore, the recirculation is effected with each arrival of a new standardized data packet. In the interim, however, the binary "1" valued charge packet is provided as an output at each clock interval from the first output channel. If the input represents binary "0", the floating gate does not inhibit transfer and a charge packet is not provided at the first output channel inasmuch as there is no overflow. Instead, an output charge packet is transferred out the second output channel to provide the complement of the data signal.

摘要翻译： 用于数字电荷耦合系统的电路提供输入二进制值的连续指示，直到复位为止，无需定时延迟，而不会导致电荷分组的退化。 将数据输入电荷包提供给存储电极，并且还以系统的数据速率向存储电极提供一系列标准化的电荷包。 锁存电路在连续的标准化充电分组到达之间的内部循环中循环运行。 输入电荷分组和标准化电荷分组的同时存在导致在第一输出数据信道中的屏障上的电荷溢出。 该溢出引起浮动栅电极，其将第一输出通道与第二输出通道相互连接，以阻止基本电荷分组转出第二输出通道。 它还使得基本的电荷包作为数据输入返回到存储电极。 因此，当基本电荷分组代表二进制“1”时，再次进行随着新的标准化数据分组的到达。 然而，在此期间，二进制“1”值充电分组作为从第一输出通道的每个时钟间隔的输出提供。 如果输入表示二进制“0”，则浮动门不阻止传输，并且由于没有溢出，因此在第一输出通道上不提供充电分组。 相反，输出电荷分组被传送出第二输出通道以提供数据信号的补码。

公开(公告)号：US4237389A

公开(公告)日：1980-12-02

申请号：US938911

申请日：1978-09-01

申请人： Reginald A. Allen

发明人： Reginald A. Allen

IPC分类号： G11C19/28 ,  H01L29/768 ,  H01L29/78

CPC分类号： H01L29/76875 ,  G11C19/285 ,  G11C19/287

摘要： A charge coupled device channel crossover circuit transfers charge packets in each of two different intersecting channels during each of a succession of transfer intervals defined by a pair of clocking signals of opposite phase and a pair of clock signal related pulse trains applied to various electrodes of the crossover circuit to provide changing potential biases. The crossover circuit includes a common transfer area at the intersection of the two channels, a pair of transfer gates within each channel on opposite sides of the transfer area and a pair of storage areas within each channel on opposite sides of the transfer gates from the transfer area. During each transfer interval a charge packet introduced at the input end of one of the channels is transferred through the intersection to the output end of the channel by the changing potential biases, following which a charge packet introduced into the input end of the other channel is transferred through the intersection to the output end of the other channel by bias level changes. The changes in bias level provided by the clocking signals and the pulse trains advance the charge packets through the intersection without interference from one another and so that each charge packet is prevented from traveling in a wrong direction or from entering the other one of the channels.

摘要翻译： 电荷耦合器件通道交叉电路在由一对相反相位的时钟信号和一对与时钟信号相对应的时钟信号相对应的一系列传输间隔的每一个传输期间，在两个不同的相交信道中的每一个中传送电荷包 交叉电路提供变化的潜在偏差。 交叉电路包括在两个通道的相交处的公共传输区域，在传输区域的相对侧上的每个通道内的一对传输门和在传输门的相对侧的每个通道内的一对存储区域 区。 在每个传送间隔期间，在其中一个信道的输入端引入的电荷包通过交点传送到通道的输出端，该变化的电位偏置，随后引入另一通道的输入端的电荷包是 通过偏移电平变化通过交叉路口转移到另一个通道的输出端。 由时钟信号和脉冲串提供的偏置电平的变化使得充电分组通过交叉点而彼此不受干扰，从而防止每个充电分组在错误的方向上行进或不进入另一个信道。

公开(公告)号：US4135104A

公开(公告)日：1979-01-16

申请号：US856780

申请日：1977-12-02

申请人： Reginald A. Allen

发明人： Reginald A. Allen

IPC分类号： G11C11/56 ,  G06F7/50 ,  G06F7/501 ,  G11C19/28 ,  G11C27/04 ,  H01L21/8247 ,  H01L29/768 ,  H01L29/788 ,  H01L29/792 ,  H03H11/26 ,  H03K19/08 ,  H03K19/21 ,  H01L27/10 ,  H01L29/78 ,  H03K5/18

CPC分类号： G06F7/501 ,  G11C19/285 ,  H01L29/76825 ,  H03K19/0806 ,  H03K19/21 ,  G06F2207/4808

摘要： The problem of gradual dissipation of charge in charge packets in charge-coupled devices (CCDs) as the packets are successively shifted is overcome by a regenerator circuit which also provides a basic structure for effecting elemental logic and arithmetic functions. A standardized charge packet is injected along with a digitally valued but somewhat diminished charge packet into a potential well under a storage electrode arranged to retain a single charge packet. Overflow from the storage electrode region that represents only some part of a full charge packet is detected by a master sensing gate that controls a slave gate forming a shunt path for the full charge packet and that is normally maintained in a transfer state. The slave gate shifts to a barrier state when the overflow packet is present, however, permitting the full charge packet to advance along another electrode path. Consequently, when a diminished charge packet having an assigned binary value is applied to the regenerator circuit, a full charge packet representing the same binary value is transferred out, and without inversion. In the absence of a charge packet at the binary input indicating the alternate binary value, the unitary charge under the storage electrode is directed out the shunt path. Advantageous arrangements are provided for in-line transfer of the data signal, sequential advance of the charge packets and dissipation of charge residues. By appropriate use of additional input transfer gates and output transfer gates, the regenerator circuit serves as a basic unit which can provide fundamental logical and digital functions needed in digital systems, including OR gates, AND gates, EXCLUSIVE-OR gates, half adders and full adders.

摘要翻译： 随着分组连续移位，电荷耦合器件（CCD）中的电荷分组中的电荷逐渐耗散的问题被再生器电路克服，再生器电路也提供用于实现元件逻辑和算术功能的基本结构。 将标准化的电荷包与数字值但稍微减小的电荷包一起注入到设置成保持单个电荷包的存储电极下方的势阱中。 来自仅表示完全充电分组的一部分的存储电极区域的溢出由主感测门来检测，该主感测门控制形成用于完全充电分组的分流路径的从门，并且通常保持在传输状态。 当存在溢出包时，从门转移到屏障状态，然而，允许完全充电分组沿另一个电极路径前进。 因此，当具有分配的二进制值的减小的电荷包被应用于再生器电路时，表示相同二进制值的完全充电分组被传送出去，而不会反转。 在没有指示二进制值的二进制输入的电荷分组的情况下，存储电极下的单位电荷被引出分流路径。 提供有利的布置用于数据信号的在线传输，电荷分组的顺序提前和电荷残留的耗散。 通过适当地使用额外的输入传输门和输出传输门，再生器电路用作可以提供数字系统中所需的基本逻辑和数字功能的基本单元，包括OR门，AND门，EXCLUSIVE-OR门，半加法器和满 加法器

公开(公告)号：US4943931A

公开(公告)日：1990-07-24

申请号：US189438

申请日：1988-05-02

申请人： Reginald A. Allen

发明人： Reginald A. Allen

IPC分类号： G06N3/063

CPC分类号： G06N3/063

摘要： An artificial neural system employs digital elements that may be fabricated using state of the art technology. The system includes a plurality of digital neural processors, each of the processors containing at least one register for storing a number; a signal is applied to the register to selectively increment or decrement the number stored in the register; circuitry is provided for resetting the register and for processing the number stored in the register. The neural system is trained by incrementing and/or decrementing numbers stored in the registers.

摘要翻译： 人造神经系统采用可以使用最先进技术制造的数字元件。 该系统包括多个数字神经处理器，每个处理器包含至少一个用于存储数字的寄存器; 信号被施加到寄存器以选择性地增加或减少存储在寄存器中的数字; 电路用于复位寄存器和处理存储在寄存器中的数字。 通过递增和/或减少存储在寄存器中的数字来训练神经系统。

公开(公告)号：US4249092A

公开(公告)日：1981-02-03

申请号：US83042

申请日：1979-10-09

申请人： Reginald A. Allen

发明人： Reginald A. Allen

IPC分类号： H03B19/00 ,  H03K23/46 ,  G11C19/28 ,  H01L29/78

CPC分类号： H03K23/46 ,  H03B19/00

摘要： A charge coupled device (CCD) frequency divider circuit for dividing the frequency of an input signal comprises a CCD having main, drain, and feedback channels. Input signal charge is injected during each cycle of the input signal into a potential well under a storage electrode that retains a predetermined quantity of charge. Overflow from the storage electrode is detected by a sensing electrode that is normally maintained in a transfer state, causing the sensing electrode to switch to a barrier state. This allows the predetermined quantity of charge to advance to an output while the overflow is dumped out by the drain channel. However, when no overflow is present, the sensing electrode causes the input charge to be transferred into the feedback channel which circulates it to the storage electrode to combine with another input charge received by the storage electrode during a subsequent cycle of the input signal. The feedback channel includes delay electrodes which delay the charge in the feedback channel from combining with the input charge until a predetermined number of cycles of the input signal have passed. The frequency of the input signal is divided by an even number dependent upon the number of cycles by which the delay electrodes delay the charge in the feedback channel from combining with a new input charge to give a whole number of output cycles. Initialization of the circuit may also be accomplished by adding to or dumping the charge that is circulating in the feedback channel.

摘要翻译： 用于分频输入信号的电荷耦合器件（CCD）分频器电路包括具有主，漏和反馈通道的CCD。 在输入信号的每个周期期间将输入信号电荷注入到保持预定量的电荷的存储电极下面的势阱中。 通过通常保持在传送状态的感测电极来检测来自存储电极的溢出，使感测电极切换到阻挡状态。 这允许预定量的电荷前进到输出，同时溢出被排放通道排出。 然而，当没有溢出时，感测电极使得输入电荷被转移到反馈通道中，该反馈通道在输入信号的后续周期期间将其循环到存储电极以与由存储电极接收的另一个输入电荷组合。 反馈通道包括延迟电极，其延迟反馈通道中的电荷与输入电荷的组合，直到输入信号的预定数量的循环已经过去。 输入信号的频率除以偶数，这取决于延迟电极延迟反馈通道中的电荷与新输入电荷的组合的周期数，以给出整数个输出周期。 电路的初始化也可以通过添加或倾倒在反馈通道中循环的电荷来实现。