System for direct access to a memory associated with a microprocessor data processing device comprising a direct access interface for introducing or extracting data in the memory during interruptions of the connection between the processing device and the memory, and a buffer interface operable during a portion of the access time of the processing device to the memory, to supply data addresses contained in the memory originating from the processing device and to enable circulation of corresponding data between the processing device and the memory, and during the remainder of the access time of the processing device, to the end of the access time, to store data transferred from the memory and to prevent transmission of data to the memory. A logic circuit controls inhibition of the buffer interface or of the direct access interface and, during the periods of inhibition of the buffer interface, permits the circulation of data and of addresses between the direct access interface and the memory.