发明授权
- 专利标题: Digital signal state analyzer and display
- 专利标题(中): 数字信号状态分析仪和显示屏
-
申请号: US41361申请日: 1979-05-22
-
公开(公告)号: US4250562A公开(公告)日: 1981-02-10
- 发明人: George A. Haag , Douglas Fogg , Gordon A. Greenley , Steve A. Shepard , F. Duncan Terry
- 申请人: George A. Haag , Douglas Fogg , Gordon A. Greenley , Steve A. Shepard , F. Duncan Terry
- 申请人地址: CA Palo Alto
- 专利权人: Hewlett-Packard Company
- 当前专利权人: Hewlett-Packard Company
- 当前专利权人地址: CA Palo Alto
- 主分类号: G06F11/25
- IPC分类号: G06F11/25 ; G06F3/05 ; G06F3/153
摘要:
A general purpose logic state analyzer selectively stores, formats and displays a digital signal representing a sequence of data states input thereto and provides a graphical display of the stored data states and a count of selected events occurring intermediate to the occurrence of the data states stored. Selective storage of the input data states is provided by comparing the input data states to a preselected sequence of first qualifier state conditions and enabling the storage of input data states in response to the satisfaction of the preselected sequence. Storage is further qualified by storing only data states which individually meet one of a preselected set of second qualifier state conditions. Selective formatting of the stored data states is provided by converting the stored data states in response to selectable assignments of contiguous sets of bits of each stored data state to logical fields, a selectable concatenation of the logical fields, and to radices selected for each of the respective logical fields. The converted stored data states can be displayed as a formatted listing or as a graphical display. In the graphical display the stored data bits corresponding to a selected logical field are interpreted as a binary magnitude and plotted as the ordinate and the chronological storage location is plotted as the ordinate and the chronological storage location is plotted as the abscissa on a cartesian coordinate system. A count of selected events is obtained from the contents of a binary counter and stored in a second memory in parallel with the storing of each data state. This counter can be incremented selectively in response to either an internal clock or in response to the detection of an input state satisfying a selected count-qualifier state condition.
公开/授权文献
- USD372986S Combination tree stand and game carrier 公开/授权日:1996-08-20
信息查询