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公开(公告)号：US4495599A
公开(公告)日：1985-01-22
申请号：US456155
申请日：1983-01-06
CPC分类号： G06F11/34 , G06F11/2205
摘要： A logic state analyzer monitors an ongoing succession of logic states occurring in a collection of n-many digital signals, and stores in a memory a set of logic states selected from the ongoing succession. A logic state is any one of the 2.sup.n -1 possible patterns the n-many digital signals may exhibit. The memory is of some convenient fixed number of locations, and once the memory is filled the oldest stored logic states are overwritten as the newest logic states are stored. Various storage qualification criteria may be specified, in which case an individual logic state is not stored unless it meets those criteria. Upon recognition of a specified trigger condition in the succession of logic states the logic state analyzer stores an operator selectable number of additional logic states, after which the monitoring and storing of logic states ceases and the stored contents of the memory are displayed. The trigger condition may be the detection of a designated sequence of selected logic states. A sequence detector monitors the ongoing succession of logic states. To satisfy the sequence and thus meet the trigger condition the first logic state in the sequence must occur and be subsequently followed by the next logic state in the sequence, and so on, until all selected logic states in the designated sequence have occurred. It may also be required that each logic state in the sequence be detected a selected number of times before an occurrence of the next logic state in the sequence can contribute toward satisfaction of the sequence. A logic state may be designated as a restart state whose occurrence nullifies any partial satisfaction of the sequence and causes the process of sequence satisfaction to begin afresh.
摘要翻译： 逻辑状态分析器监视在n个数字信号的集合中发生的正在进行的一系列逻辑状态，并且在存储器中存储从正在进行的继承中选择的一组逻辑状态。 逻辑状态是n多个数字信号可能呈现的2n-1个可能模式中的任何一个。 存储器具有一些方便的固定数量的位置，并且一旦存储器被填充，则存储最新的逻辑状态的最旧存储的逻辑状态被覆盖。 可以指定各种存储资格标准，在这种情况下，除非满足这些标准，否则不存储单独的逻辑状态。 在逻辑状态的连续识别中指定的触发条件之后，逻辑状态分析器存储操作者可选数量的附加逻辑状态，之后停止监视和存储逻辑状态，并且显示存储器的存储内容。 触发条件可以是检测所选逻辑状态的指定序列。 序列检测器监视正在进行的逻辑状态序列。 为了满足序列并因此满足触发条件，序列中的第一逻辑状态必须发生，并且随后将在序列中跟随下一个逻辑状态，依此类推，直到指定序列中的所有选定的逻辑状态发生。 还可能需要在序列中的下一逻辑状态的发生可以有助于满足序列之前，在序列中的每个逻辑状态被检测到选定的次数。 逻辑状态可以被指定为重新开始状态，其发生使得序列的任何部分满意度无效，并使序列满足的处理重新开始。
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公开(公告)号：US4480317A
公开(公告)日：1984-10-30
申请号：US456218
申请日：1983-01-07
CPC分类号： G06F11/2205 , G06F11/34
摘要： A logic state analyzer monitors an ongoing succession of states occurring in a collection of digital signals, and stores in a memory a set of states selected from the ongoing succession. The memory is of some convenient fixed number of locations, and once the memory is filled the oldest stored states are overwritten as the newest states are stored. Various storage qualification criteria may be specified, in which case an individual state is not stored unless the state meets those criteria. Upon recognition of a specified trigger condition in the succession of states the logic state analyzer stores an operator selectable number of additional states. The trigger condition may be as simple as the occurrence of a single specified state or may be as complex as the satisfaction of a sequence of specified states. The resulting collectivity of states stored in the memory may be termed a captured trace. Each of the states in the captured trace is a pattern of logical values for the individual digital signals in the collection thereof. That is, each state is also a bit pattern, and is expressable as a magnitude in a selected radix such as binary, octal, or hexadecimal. The states of the captured trace also possess the natural chronological order in which they were stored into the memory. The captured trace is presented as a graph in cartesian coordinates. The graph is a series of points, each representing a state in the captured trace. The ordinate of each point is the magnitude of the state rendered in a selected radix. The abscissa of each point is the ordinal number indicative of the state's chronological position in the captured trace.
摘要翻译： 逻辑状态分析器监视在数字信号的集合中发生的持续的状态的一系列状态，并且在存储器中存储从正在进行的继承中选择的一组状态。 存储器具有一些方便的固定数量的位置，并且一旦存储器被填充，则存储最新的状态时，最旧的存储状态被覆盖。 可以指定各种存储资格标准，在这种情况下，除非国家符合这些标准，否则不存储单个状态。 在逻辑状态分析器识别状态的连续状态中指定的触发条件时，存储操作者可选数量的附加状态。 触发条件可以与单个指定状态的发生一样简单，或者可能与指定状态序列的满足一样复杂。 存储在存储器中的状态的所得集合可以被称为捕获的迹线。 捕获的迹线中的每个状态是其收集中的各个数字信号的逻辑值的模式。 也就是说，每个状态也是一个位模式，并且可以被表达为所选择的基数（例如二进制，八进制或十六进制）中的大小。 捕获的痕迹的状态也具有自然的时间顺序，它们被存储到记忆体中。 捕获的轨迹以笛卡尔坐标表示为图形。 该图是一系列点，每个点表示捕获的轨迹中的状态。 每个点的纵坐标是在所选基数中呈现的状态的大小。 每个点的横坐标是指示状态在捕获轨迹中的时间顺序位置的序数。
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公开(公告)号：US4303987A
公开(公告)日：1981-12-01
申请号：US41363
申请日：1979-05-22
CPC分类号： G06F11/25
摘要： A general purpose logic state analyzer selectively stores, formats and displays a digital signal representing a sequence of data states input thereto and provides a graphical display of the stored data states and a count of selected events occurring intermediate to the occurrence of the data states stored. Selective storage of the input data states is provided by comparing the input data states to a preselected sequence of first qualifier state conditions and enabling the storage of input data states in response to the satisfaction of the preselected sequence. Storage is further qualified by storing only data states which individually meet one of a preselected set of second qualifier state conditions. Selective formatting of the stored data states is provided by converting the stored data states in response to selectable assignments of contiguous sets of bits of each stored data state to logical fields, a selectable concatenation of the logical fields, and to radicies selected for each of the respective logical fields. The converted stored data states can be displayed as a formatted listing or as a graphical display. In the graphical display the stored data bits corresponding to a selected logical field are interpreted as a binary magnitude and plotted as the ordinate and the chronological storage location is plotted as the ordinate and the chronological storage location is plotted as the abscissa on a cartesian coordinate system. A count of selected events is obtained from the contents of a binary counter and stored in a second memory in parallel with the storing of each data state. This counter can be incremented selectively in response to either an internal clock or in response to the detection of an input data state satisfying a selected count-qualifier state condition.
摘要翻译： 通用逻辑状态分析器选择性地存储，格式化和显示表示输入到其中的数据状态序列的数字信号，并且提供存储的数据状态的图形显示和存储的数据状态出现中间的选定事件的计数。 输入数据状态的选择性存储是通过将输入数据状态与预选的第一限定条件状态序列进行比较并且响应于预选序列的满足而实现输入数据状态的存储来提供的。 通过仅存储单独满足预选的第二限定条件状态集合的数据状态来进一步限定存储。 存储的数据状态的选择性格式化是通过将存储的数据状态响应于每个存储的数据状态的连续位组合的可选分配转换为逻辑字段，逻辑字段的可选连接以及为每个 各自的逻辑字段。 转换的存储数据状态可以显示为格式化列表或图形显示。 在图形显示中，对应于所选择的逻辑字段的存储的数据位被解释为二进制幅度并作为纵坐标绘制，按时间顺序存储位置作为纵坐标绘制，按时间顺序存储位置作为横坐标绘制在笛卡尔坐标系上 。 选择事件的计数从二进制计数器的内容获得，并且与每个数据状态的存储并行存储在第二存储器中。 该计数器可以响应于内部时钟或响应于检测满足所选择的计数限定条件状态的输入数据状态而选择性递增。
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4.发明授权Method and apparatus for selecting and setting the mode of operation for a mechanism 失效用于选择和设置机构的操作模式的方法和装置
公开(公告)号：US4479197A
公开(公告)日：1984-10-23
申请号：US454387
申请日：1982-12-29
CPC分类号： G06F11/2205 , G06F11/34 , Y10S715/97
摘要： The operating modes and parameters of a logic state analyzer are selected by user interaction with a menu displayed upon a CRT. At the highest level of control the user may specify which menu is of interest, should there be more than one. The selected menu is displayed and contains mode selection fields whose labels indicate the various modes that are presently selected. Different modes are selected by positioning a cursor to the associated selection field and then pressing a mode selection key. Each such activation causes the next mode in a sequence of modes, associated with that particular field, to be the selected mode of operation. A descriptive label or phase corresponding to the selected mode is displayed as part of the selection field containing the cursor. The modes and their associated labels are linked in a cyclic order, and repeated activation of the field select key will cycle through the cyclic sequence indefinitely, revealing to the operator what his choices are, as well as indicating the present choice. The cursor may be positioned in random order among several such mode selection fields, but only one field select key is needed, as its above-described action pertains to whichever field contains the cursor. The cursor may also be positioned to parameter entry fields associated with selected modes, and a collection of parameter entry keys allows entry of associated parameters.
摘要翻译： 逻辑状态分析器的操作模式和参数通过用户与CRT上显示的菜单进行交互来选择。 在最高级别的控制下，用户可以指定哪个菜单是感兴趣的，如果有多于一个。 显示所选菜单，并包含标签指示当前选择的各种模式的模式选择字段。 通过将光标定位到关联的选择字段，然后按模式选择键来选择不同的模式。 每个这样的激活使得与该特定字段相关联的一系列模式中的下一个模式成为所选择的操作模式。 对应于所选模式的描述性标签或相位显示为包含光标的选择字段的一部分。 模式及其相关联的标签以循环顺序链接，并且场选择键的重复激活将无限期地循环遍历循环序列，向操作者显示他的选择以及指示当前选择。 光标可以在多个这样的模式选择字段之间以随机顺序定位，但是仅需要一个字段选择键，因为其上述动作涉及包含光标的哪个字段。 光标也可以被定位到与所选模式相关联的参数输入字段，并且参数输入键的集合允许输入相关参数。
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公开(公告)号：US4455624A
公开(公告)日：1984-06-19
申请号：US457599
申请日：1983-01-13
CPC分类号： G06F11/2205 , G06F11/34
摘要： Ongoing succession of states occurring in a collection of digital signals is monitored by a logic state analyzer which stores either all such states or a selected subset thereof meeting certain qualification criteria. The memory into which the states are stored is updated with oldest stored states being overwritten as the newest states are stored, the collectivity of which may be termed a captured trace. The above-mentioned qualification and sequential criteria are termed a trace specification. The utility of such a trace in a logic state analyzer is enhanced by allowing the user to divide the collection of digital signals into groups of related signals, assign symbolic labels to the groups, and indicate a radix for each group. Such division, assignment and indication may be termed a format specification. Subsequent trace specifications as well as the displayed or printed form of the trace itself then incorporate the format specification.
摘要翻译： 在数字信号收集中发生的状态的持续继续由逻辑状态分析器监视，逻辑状态分析器存储所有这些状态或其所选择的子集满足某些资格标准。 存储状态的存储器被更新，最旧的存储状态被更新，因为最新状态被存储，其集合可以被称为捕获的跟踪。 上述资格和顺序标准被称为追踪规范。 通过允许用户将数字信号的集合划分成相关信号的组，将符号标签分配给组，并为每个组指示基数，来增强逻辑状态分析器中这种轨迹的用途。 这种划分，分配和指示可以被称为格式规范。 随后的跟踪规范以及跟踪本身的显示或打印形式，然后纳入格式规范。
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6.发明授权Apparatus and method for indicating a minimum degree of activity of digital signals 失效用于指示数字信号的最小活动程度的装置和方法
公开(公告)号：US4293925A
公开(公告)日：1981-10-06
申请号：US43987
申请日：1979-05-31
CPC分类号： G01R31/3177
摘要： A general purpose logic state analyzer selectively stores, formats and displays a digital signal representing a sequence of data states input thereto and provides a graphical display of the stored data states and a count of selected events occurring intermediate to the occurrence of the data states stored. Selective storage of the input data states is provided by comparing the input data states to a preselected sequence of first qualifier state conditions and enabling the storage of input data states in response to the satisfaction of the preselected sequence. Storage is further qualified by storing only data states which individually meet one of a preselected set of second qualifier state conditions. Selective formatting of the stored data states is provided by converting the stored data states in response to selectable assignments of contiguous sets of bits of each stored data state to logical fields, a selectable concatenation of the logical fields, and to radicies selected for each of the respective logical fields. The converted stored data states can be displayed as a formatted listing or as a graphical display. In the graphical display the stored data bits corresponding to a selected logical field are interpreted as a binary magnitude and plotted as the ordinate and the chronological storage location is plotted as the ordinate and the chronological storage location is plotted as the abscissa on a cartesian coordinate system. A count of selected events is obtained from the contents of a binary counter and stored in a second memory in parallel with the storing of each data state. This counter can be incremented selectively in response to either an internal clock or in response to the detection of an input data state satisfying a selected count-qualifier state condition.
摘要翻译： 通用逻辑状态分析器选择性地存储，格式化和显示表示输入到其中的数据状态序列的数字信号，并且提供存储的数据状态的图形显示和存储的数据状态出现中间的选定事件的计数。 输入数据状态的选择性存储是通过将输入数据状态与预选的第一限定条件状态序列进行比较并且响应于预选序列的满足而实现输入数据状态的存储来提供的。 通过仅存储单独满足预选的第二限定条件状态集合的数据状态来进一步限定存储。 存储的数据状态的选择性格式化是通过将存储的数据状态响应于每个存储的数据状态的连续位组合的可选分配转换为逻辑字段，逻辑字段的可选连接以及为每个 各自的逻辑字段。 转换的存储数据状态可以显示为格式化列表或图形显示。 在图形显示中，对应于所选择的逻辑字段的存储的数据位被解释为二进制幅度并作为纵坐标绘制，按时间顺序存储位置作为纵坐标绘制，按时间顺序存储位置作为横坐标绘制在笛卡尔坐标系上 。 选择事件的计数从二进制计数器的内容获得，并且与每个数据状态的存储并行存储在第二存储器中。 该计数器可以响应于内部时钟或响应于检测满足所选择的计数限定条件状态的输入数据状态而选择性递增。
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公开(公告)号：US4250562A
公开(公告)日：1981-02-10
申请号：US41361
申请日：1979-05-22
CPC分类号： G06F11/25
摘要： A general purpose logic state analyzer selectively stores, formats and displays a digital signal representing a sequence of data states input thereto and provides a graphical display of the stored data states and a count of selected events occurring intermediate to the occurrence of the data states stored. Selective storage of the input data states is provided by comparing the input data states to a preselected sequence of first qualifier state conditions and enabling the storage of input data states in response to the satisfaction of the preselected sequence. Storage is further qualified by storing only data states which individually meet one of a preselected set of second qualifier state conditions. Selective formatting of the stored data states is provided by converting the stored data states in response to selectable assignments of contiguous sets of bits of each stored data state to logical fields, a selectable concatenation of the logical fields, and to radices selected for each of the respective logical fields. The converted stored data states can be displayed as a formatted listing or as a graphical display. In the graphical display the stored data bits corresponding to a selected logical field are interpreted as a binary magnitude and plotted as the ordinate and the chronological storage location is plotted as the ordinate and the chronological storage location is plotted as the abscissa on a cartesian coordinate system. A count of selected events is obtained from the contents of a binary counter and stored in a second memory in parallel with the storing of each data state. This counter can be incremented selectively in response to either an internal clock or in response to the detection of an input state satisfying a selected count-qualifier state condition.
摘要翻译： 通用逻辑状态分析器选择性地存储，格式化和显示表示输入到其中的数据状态序列的数字信号，并且提供存储的数据状态的图形显示和存储的数据状态出现中间的选定事件的计数。 输入数据状态的选择性存储是通过将输入数据状态与预选的第一限定条件状态序列进行比较并且响应于预选序列的满足而实现输入数据状态的存储来提供的。 通过仅存储单独满足预选的第二限定条件状态集合的数据状态来进一步限定存储。 存储的数据状态的选择性格式化是通过将存储的数据状态响应于每个存储的数据状态的连续位组的可选分配转换为逻辑字段，逻辑字段的可选连接以及为每个 各自的逻辑字段。 转换的存储数据状态可以显示为格式化列表或图形显示。 在图形显示中，对应于所选择的逻辑字段的存储的数据位被解释为二进制幅度并作为纵坐标绘制，按时间顺序存储位置作为纵坐标绘制，按时间顺序存储位置作为横坐标绘制在笛卡尔坐标系上 。 选择事件的计数从二进制计数器的内容获得，并且与每个数据状态的存储并行存储在第二存储器中。 该计数器可以响应于内部时钟或响应于检测到满足所选计数限定条件状态的输入状态而选择性递增。
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公开(公告)号：US4500895A
公开(公告)日：1985-02-19
申请号：US490754
申请日：1983-05-02
CPC分类号： B41J2/17526 , B41J2/14024 , B41J2/17513 , B41J2002/14387
摘要： A thermal ink jet head is disclosed in which the jetting resistors, fluid interconnections, ink reservoir, electrical connections, and jetting orifices are fully integrated to provide an inexpensive, disposable jetting head. The entire hydraulic ink system is sealed to eliminate user interaction with the liquid ink, and ink can only exit the head via the jetting orifices under the influence of the jetting resistors. Once the ink is expended the user disposes with the old head and installs a new one by breaking and making a simple mechanical and low voltage electrical connection.
摘要翻译： 公开了一种热喷墨头，其中喷射电阻器，流体互连，墨水储存器，电连接和喷射孔完全集成以提供便宜的一次性喷射头。 整个液压油墨系统被密封以消除用户与液体油墨的相互作用，并且油墨只能在喷射电阻器的影响下经由喷射孔排出头部。 一旦墨水消耗，用户将旧的头部放置并通过断开并进行简单的机械和低压电气连接来安装新的墨水。
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9.发明授权Logic state analyzer with time and event count measurement between states 失效逻辑状态分析器，具有状态之间的时间和事件计数测量
公开(公告)号：US4445192A
公开(公告)日：1984-04-24
申请号：US459425
申请日：1983-01-20
CPC分类号： G06F11/2205 , G06F11/34
摘要： A logic state analyzer monitors the ongoing succession of states occurring in a collection of digital signals, and stores in a memory either all such states or a selected subset thereof meeting certain qualification criteria. The oldest stored states are overwritten as the newest states are stored. Upon recognition of some trigger condition the logic state analyzer will subsequently store a preselected number of additional states, the collectivity of which may be termed the captured trace. The utility of such a trace in a logic state analyzer is enhanced by equipping the analyzer with a counting mechanism selectively responsive to a high speed clock signal or a programmable state detector. In the former case the counter operates as a timer whose value may represent either the elapsed time between consecutive states in the trace or between each state in the trace and an origin along a time axis. In the latter case the user identifies a state or event of interest and the counter records the number of times that state occurs between the stored states of the trace. In both cases the values of the times or event counts are stored as part of the trace and are displayed in correlated relation to the state data therein.
摘要翻译： 逻辑状态分析器监视在数字信号集合中发生的持续状态的连续状态，并将所有这样的状态或其选定的子集存储在存储器中以满足某些限定条件。 最旧的存储状态被存储的最新状态被覆盖。 当识别到一些触发条件时，逻辑状态分析器随后将存储预选数量的附加状态，其集合可被称为捕获的迹线。 通过为分析仪配备选择性地响应于高速时钟信号或可编程状态检测器的计数机构来增强逻辑状态分析器中这种迹线的用途。 在前一种情况下，计数器作为定时器运行，其值可以表示迹线中的连续状态之间或轨迹中的每个状态之间的经过时间和沿着时间轴的原点。 在后一种情况下，用户识别感兴趣的状态或事件，并且计数器记录状态发生在跟踪的存储状态之间的次数。 在这两种情况下，时间或事件计数的值都作为跟踪的一部分存储，并以与其中的状态数据相关的关系显示。
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公开(公告)号：US4373193A
公开(公告)日：1983-02-08
申请号：US210462
申请日：1980-11-25
CPC分类号： G06F11/25
摘要： A logic state analyzer stores into a data acquisition memory only state data meeting preselected qualification state criteria chosen to weed out state data not of interest among the totality of states occuring within a collection of digital signals. The data acquisition memory retains only the last m-many states stored therein. A selectable integer k, o.ltoreq.k.ltoreq.m, determines how many additional storage operations are performed for qualified state data following the detection of a preselected trigger condition. The actual number of states occurring in the collection of digital signals after the trigger condition but before the storage of the kth qualified data state can be many times the value of k. Qualifying the state data prior to storage allows a modest size data acquisition memory to do the work of a much larger memory and spares the user the task of sorting through much state data known not to be of interest. The preselected qualification criteria may include don't-cares in the definition of the qualification state, as well as the logical OR'ing of a plurality of such qualification states.
摘要翻译： 逻辑状态分析器仅存储数据采集存储器中的状态数据，该状态数据满足预先选定的资格状态标准，以便在数字信号集合内发生的状态的总数中除去不感兴趣的状态数据。 数据采集存储器仅保存存储在其中的最后多个状态。 可选择的整数k，o
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