发明授权
- 专利标题： Power on and low voltage reset circuit
- 专利标题（中）： 上电和低压复位电路
-
申请号： US35044申请日： 1979-05-01
-
公开(公告)号： US4296338A公开(公告)日： 1981-10-20
- 发明人: James S. Thomas
- 申请人： James S. Thomas
- 申请人地址： IL Schaumburg
- 专利权人： Motorola, Inc.
- 当前专利权人： Motorola, Inc.
- 当前专利权人地址： IL Schaumburg
- 主分类号： H03K17/22
- IPC分类号： H03K17/22 ; H03K5/153 ; H02J13/00 ; H03K5/24 ; H03K17/687
摘要：
An NMOS power on/low voltage reset circuit provides a substantially instantaneous reset enabling signal when a predetermined fraction of the power supply voltage falls below a predetermined reference voltage. In addition, an external capacitor is discharged. A second reset enabling signal is extended until the capacitor is again charged to a predetermined voltage thus allowing the clock oscillators of a microcomputer sufficient time to stabilize. Self test means are also provided. The reset circuit is implemented on the microcomputer chip.
公开/授权文献
- US5974820A Refrigerant cylinder jacket construction 公开/授权日：1999-11-02
信息查询
IPC分类:
