发明授权
- 专利标题： Burst-error correcting system
- 专利标题（中）： 突发纠错系统
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申请号： US218256申请日： 1980-12-19
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公开(公告)号： US4355392A公开(公告)日： 1982-10-19
- 发明人: Toshitada Doi , Akira Iga
- 申请人： Toshitada Doi , Akira Iga
- 申请人地址： JPX Tokyo
- 专利权人： Sony Corporation
- 当前专利权人： Sony Corporation
- 当前专利权人地址： JPX Tokyo
- 优先权： JPX53-47247 19780421
- 主分类号： G06F11/10
- IPC分类号： G06F11/10 ; G11B20/18 ; H03M13/00 ; H03M13/27 ; H04L1/00
摘要：
In a digital signal transmission system, a predetermined number of words of digital information signals are added bit by bit in a modulo 2 adder to produce a first parity signal. The information signals and the first parity signal are delayed so as to have different delay times to each other, and the signals thus delayed are again added bit by bit in a modulo-2 adder to produce a second parity signal. The predetermined number of words of information signals and first and second parity signals are serially transmitted through a transmission line.
公开/授权文献
- US5492717A Pear processing method 公开/授权日：1996-02-20
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