An absolute differentiator receives a self-clocking digital input signal, and its output is applied to a series of delay elements. The outputs of the differentiator and the delay elements are coupled to an OR-gate. The output of the OR-gate is applied to a phase-locked loop to produce a recovered clock signal. The delay elements can be variable with a delay controlled by an output signal from the phase-locked loop, to thereby track a varying center frequency of the digital input signal.