An ac coupled, chopper stabilized differential comparator circuit characterized receiving a differential signal voltage applied between a signal input terminal and a reference signal input terminal, providing differential outputs at a first and second differential output terminal and being characterized as operating from a voltage source with respect to a reference potential comprising: amplifier means, characterized by a first stage differential amplifier having, a first channel amplifier having an input terminal and an output terminal. The first channel amplifier output terminal is connected to the first differential output terminal. The first stage differential amplifier also has a second channel amplifier having an input terminal and an output terminal. The second channel amplifier output terminal is connected to the second differential output terminal. The gain of the second channel amplifier is essentially equal to the gain of the first channel amplifier. A first channel input capacitor having a first and second terminal is included, the second terminal being connected to the first channel amplifier input terminal. A second channel input capacitor is also included, having a first and second terminal, the second terminal being connected to the second channel amplifier input terminal. A clock signal means is included, having a first clock signal and a second clock signal, along with means responsive to the first clock signal for connecting the first and second channel amplifier output terminals to their respective input terminals. Signal input selection means is included for connecting the signal input terminal to the first channel input capacitor first terminal, and for connecting the reference signal input terminal to the second channel input capacitor first terminal, in response to only the first clock signal. The signal input selection means connects the signal input terminal to the second channel input capacitor first terminal and also connects the reference signal input terminal to the first channel input capacitor first terminal in response to the second clock signal; whereby the differential signal voltage between the signal input terminal and the reference signal input terminal is amplified. The amplified differential voltage is provided as a differential output voltage between the first and second channel amplifier output terminals having reduced amplifier offset voltage error.