发明授权
- 专利标题： Oxide walled emitter
- 专利标题（中）： 氧化物壁发射体
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申请号： US542555申请日： 1983-10-17
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公开(公告)号： US4484211A公开(公告)日： 1984-11-20
- 发明人: Toyoki Takemoto , Tsutomu Fujita , Hiroyuki Sakai , Haruyasu Yamada
- 申请人： Toyoki Takemoto , Tsutomu Fujita , Hiroyuki Sakai , Haruyasu Yamada
- 申请人地址： JPX Osaka
- 专利权人： Matsushita Electric Industrial Co., Ltd.
- 当前专利权人： Matsushita Electric Industrial Co., Ltd.
- 当前专利权人地址： JPX Osaka
- 主分类号： H01L29/06
- IPC分类号： H01L29/06 ; H01L29/732 ; H01L27/04 ; H01L29/04 ; H01L29/72
摘要：
A semiconductor integrated circuit device in which the side surfaces of an emitter of an oxide isolated bipolar transistor are surrounded with insulating compounds or regions so that the capacitance between the emitter and base is lowered and a base is formed by the self-alignment so that the influence of an active base between an external base and the emitter can be made negligible. Thus the base resistance and parasitic capacitance are lowered.