A true/complement generator for generating the complement and true value of weighted address bits, preventing an address decoder from selecting several lines at the same time. It comprises two circuits (1) and (2), the first one providing the true value (.phi.), the second one providing the complement (.phi.) thereof. The means provided for preventing multiple selections from occurring, comprise in the first circuit, a transistor (T11-1) for delaying the rising edge of (.phi.) as long as it is maintained on by the level provided by resistors R11-1 and R10-2 from output .phi.. Transistor T11-2 in the second circuit prevents .phi. from going high as long as it is maintained on by the level provided by R10-1, R11-2 from .phi..