公开(公告)号：US4263518A

公开(公告)日：1981-04-21

申请号：US46529

申请日：1979-06-07

申请人： Daniel Ballatore ,  Francois Delaporte ,  Gerard Lebesnerais ,  Jean-Paul Nuez

发明人： Daniel Ballatore ,  Francois Delaporte ,  Gerard Lebesnerais ,  Jean-Paul Nuez

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L27/08 ,  H01L29/78 ,  H01L29/8605 ,  H01L27/10 ,  H01L29/76

CPC分类号： H01L29/8605 ,  H01L27/0802

摘要： Arrangements are described for correcting the voltage coefficient of resistance (VCR) of resistors integral with a semiconductor body and, more particularly, for correcting the VCR of resistors implanted in a semi-conductor body. Resistors typically comprising a resistive region of a first conductivity type formed in an isolated layer of opposite conductivity type which isolated layer, in general, includes an epitaxial layer passivated by a dielectric layer. A metal layer is formed on the dielectric layer and covers, at least partially, the resistive layer. The metal layer is brought to a suitable potential to produce opposite variations in the resistance with respect to variations created by the epitaxial layer.

摘要翻译： 描述了用于校正与半导体本体集成的电阻器的电阻（VCR）的电压系数的布置，更具体地，用于校正植入半导体体中的电阻器的VCR。 通常包括形成在相反导电类型的隔离层中的第一导电类型的电阻区域的电阻器，该绝缘层通常包括被电介质层钝化的外延层。 在电介质层上形成金属层，至少部分覆盖电阻层。 相对于由外延层产生的变化，金属层被带到适当的电位以产生相对的电阻变化。

公开(公告)号：US4529896A

公开(公告)日：1985-07-16

申请号：US448135

申请日：1982-12-09

申请人： Michel Grandguillot ,  Pierre Mollier ,  Jean-Paul Nuez

发明人： Michel Grandguillot ,  Pierre Mollier ,  Jean-Paul Nuez

IPC分类号： G11C11/413 ,  G11C8/06 ,  H03K5/151 ,  H03K5/15 ,  H03K19/088 ,  H03K19/20

CPC分类号： G11C8/06 ,  H03K5/1515

摘要： A true/complement generator for generating the complement and true value of weighted address bits, preventing an address decoder from selecting several lines at the same time. It comprises two circuits (1) and (2), the first one providing the true value (.phi.), the second one providing the complement (.phi.) thereof. The means provided for preventing multiple selections from occurring, comprise in the first circuit, a transistor (T11-1) for delaying the rising edge of (.phi.) as long as it is maintained on by the level provided by resistors R11-1 and R10-2 from output .phi.. Transistor T11-2 in the second circuit prevents .phi. from going high as long as it is maintained on by the level provided by R10-1, R11-2 from .phi..

摘要翻译： 用于产生加权地址位的补码和真值的真/补码发生器，防止地址解码器同时选择多个行。 它包括两个电路（1）和（2），第一个提供真实值（phi），第二个提供其补码（phi）。 在第一电路中，包括用于延迟（phi）的上升沿的晶体管（T11-1），只要它被电阻器R11-1和R10提供的电平保持在上，则防止发生多重选择的装置 -2从输出phi。 第二回路中的晶体管T11-2只要保持在来自phi的R10-1，R11-2提供的电平，就能防止phi变高。

公开(公告)号：US4298401A

公开(公告)日：1981-11-03

申请号：US95817

申请日：1979-11-19

申请人： Jean-Paul Nuez ,  Gerard Lebesnerais

发明人： Jean-Paul Nuez ,  Gerard Lebesnerais

IPC分类号： H01L27/04 ,  H01L21/265 ,  H01L21/822 ,  H01L29/8605 ,  H01L3/22 ,  H01L29/90

CPC分类号： H01L21/26513 ,  H01L29/8605

摘要： An implanted resistor structure for semiconductor integrated circuit devices is formed by a double ion-implantation providing a high breakdown voltage resistor.

摘要翻译： 用于半导体集成电路器件的注入电阻器结构通过提供高耐压电阻器的双离子注入形成。

公开(公告)号：US5089725A

公开(公告)日：1992-02-18

申请号：US604842

申请日：1990-10-26

申请人： Pierre Mollier ,  Jean-Paul Nuez ,  Pascal Tannhof

发明人： Pierre Mollier ,  Jean-Paul Nuez ,  Pascal Tannhof

IPC分类号： H03K19/013 ,  H03K19/086

CPC分类号： H03K19/086 ,  H03K19/013

摘要： The base circuit comprises a self-referenced preamplifier (31) of the differential type connected between first and second supply voltages and a push-pull output buffer stage connected between second and third supply voltages. The push-pull output buffer stage comprises a pull-up transistor and a pull-down transistor connected in series with the circuit output node coupled therebetween. These transistors are driven by complementary and substantially simultaneous signals S and S supplied by the preamplifier. Both branches of the preamplifier are tied at a first output node (M). The first branch comprises a logic block performing the desired logic function of the base circuit that is connected through a load rsistor to the second supply voltage. The logic block consists of three parallel-connected input NPN transistors, whose emitters are coupled together at the first output node for NOR operation. The second branch is comprised of a biasing/coupling block connected to the second supply voltage and coupled to the first output node and to the base (B) node of the pull-down transistor. This block ensures both the appropriate polarization of the nodes in DC without the need of external reference voltage generators and a low impedance path for fast signal transmission of the output signal from node M to node B in AC, when input transistors of the logic block are ON. and base nodes. An anti-saturation block (AB), consisting typically of a Schottky Barrier Diode (SBD), is useful to prevent saturation of the pull down transistor (TDN) to further speed up the circuit.

摘要翻译： 基本电路包括连接在第一和第二电源电压之间的差分类型的自参考前置放大器（31）和连接在第二和第三电源电压之间的推挽输出缓冲级。 推挽输出缓冲级包括与耦合在其间的电路输出节点串联连接的上拉晶体管和下拉晶体管。 这些晶体管由前置放大器提供的互补和基本同时的信号S和＆amp; upbar＆S驱动。 前置放大器的两个分支都连接在第一个输出节点（M）上。 第一分支包括执行通过负载晶体管连接到第二电源电压的基本电路的期望逻辑功能的逻辑块。 逻辑块由三个并联的输入NPN晶体管组成，其发射极在第一个输出节点耦合在一起用于NOR运算。 第二分支包括连接到第二电源电压并耦合到第一输出节点和下拉晶体管的基极（B）节点的偏置/耦合模块。 该块在逻辑块的输入晶体管中确保DC中节点的适当极化，而不需要外部参考电压发生器和低阻抗路径，用于在AC中将节点M到节点B的输出信号快速信号传输 上。 和基本节点。 通常由肖特基势垒二极管（SBD）组成的抗饱和块（AB）可用于防止下拉晶体管（TDN）的饱和，从而进一步加速电路。

公开(公告)号：US5010257A

公开(公告)日：1991-04-23

申请号：US493014

申请日：1990-03-13

申请人： Gerard Boudon ,  Pierre Mollier ,  Jean-Paul Nuez ,  Ieng Ong ,  Pascal Tannhof ,  Franck Wallart

发明人： Gerard Boudon ,  Pierre Mollier ,  Jean-Paul Nuez ,  Ieng Ong ,  Pascal Tannhof ,  Franck Wallart

IPC分类号： H03K17/567 ,  H03K5/007 ,  H03K19/013 ,  H03K19/0175 ,  H03K19/08 ,  H03K19/0944

CPC分类号： H03K19/0136 ,  H03K19/09448 ,  H03K5/007

摘要： According to the present invention, a CMOS interface circuit (C2) similar to a latch made by two CMOS cross coupled inverters (INV1, INV2) is placed directly on the output node (14) of conventional BICMOS logic circuit (11) operating alone in a partial swing mode. This latch is made of four FETs P5, P6, N8, N9 cross-coupled in a conventional way with the feedback loop connected to said output node (14). The partial voltage swing (VBE to VH-VBE) naturally given by the output bipolar transistors (T1, T2) mounted in a push pull configuration is reinforced to full swing (GND to VH) by the latch at the end of each transition. The state of the output node if forced by the latch because of the high driving capability due to the presence of said output bipolar transistors (T1, T2). As a result, the improved BICMOS logic circuit (D2) has an output signal (S) that ranges within the desired full swing voltage at the output terminal (15). It is a characteristic of this embodiment that the structure of CMOS interface (C2) is always independent of the logic function implemented in the conventional BICMOS logic circuit (11). More generally, the CMOS interface circuit may have various physical implementations, however, it is always comprised of CMOS FETs and it becomes active at least in one of the GND to VBE or (VH-BE) to VH range.