发明授权
- 专利标题: Functionally redundant logic network architectures
- 专利标题(中): 功能冗余逻辑网络架构
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申请号: US560109申请日: 1983-12-12
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公开(公告)号: US4551814A公开(公告)日: 1985-11-05
- 发明人: Donald W. Moore , Rick A. Verstraete
- 申请人: Donald W. Moore , Rick A. Verstraete
- 申请人地址: CA La Jolla
- 专利权人: Aerojet-General Corporation
- 当前专利权人: Aerojet-General Corporation
- 当前专利权人地址: CA La Jolla
- 主分类号: H03K19/003
- IPC分类号: H03K19/003 ; G06F11/20 ; H03K19/173
摘要:
A logic gate structure having functionally redundant architecture for enhanced production yields and reliability comprises a plurality of two-input nodes at least some of which may be programmed by control states for changing the logical function of the gate structure. Redundancy is provided by gate structure implementations in which the number of possible control states exceed the number of logic functions expected of the gate structure. Redundancy increases the probability of gate structure operation despite logic faults and renders the gate structure suitable for use in adaptable problem solving machines such as robots and pattern recognition apparatus.A number of embodiments are disclosed including three and four input variable networks. Some such embodiments include selected architectural simplifications wherein certain nodes in a network are either logically fixed or entirely omitted to reduce the number of control lines.
公开/授权文献
- US5660147A Livestock handling apparatus and method 公开/授权日:1997-08-26
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