发明授权
- 专利标题: Synchronization circuit for a Viterbi decoder
- 专利标题(中): 维特比解码器同步电路
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申请号: US511503申请日: 1983-07-06
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公开(公告)号: US4578800A公开(公告)日: 1986-03-25
- 发明人: Yutaka Yasuda , Yasuo Hirata , Shuji Murakami , Katsuhiro Nakamura , Yukitsuna Furuya
- 申请人: Yutaka Yasuda , Yasuo Hirata , Shuji Murakami , Katsuhiro Nakamura , Yukitsuna Furuya
- 专利权人: KOKUSAI DENSHIN DENWA Co Ltd 3-2 NISHISHINJUKU 2-CHOME SHINJUKU-KU TOKYO JAPAN,NEC Corp
- 当前专利权人: KOKUSAI DENSHIN DENWA Co Ltd 3-2 NISHISHINJUKU 2-CHOME SHINJUKU-KU TOKYO JAPAN,NEC Corp
- 优先权: JPX57-120941 19820712; JPX57-120942 19820712
- 主分类号: H03M13/33
- IPC分类号: H03M13/33 ; H04L7/00 ; H04L7/02 ; H04L7/04
摘要:
A Viterbi decoder synchronization circuit comprises a phase shifter for introducing a variable amount of delay time to a received bit stream of convolutional codes in response to a control signal applied thereto with respect to a word synchronization signal which is derived from the bit stream. A first detector detects maximum and minimum metric values of the Viterbi decoder. A second detector detects the difference between the detected maximum and minimum metric values for coupling to an integrator. The output of the integrator is applied to a third detector which detects when the integrator output reaches a value indicative of a word-in-sync or word-out-of-sync condition. A phase shift signal is generated in response to an output signal from the third detector and applied to the phase shifter as the control signal.
公开/授权文献
- USD342904S Clock 公开/授权日:1994-01-04
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