公开(公告)号：US4578800A

公开(公告)日：1986-03-25

申请号：US511503

申请日：1983-07-06

申请人： Yutaka Yasuda ,  Yasuo Hirata ,  Shuji Murakami ,  Katsuhiro Nakamura ,  Yukitsuna Furuya

发明人： Yutaka Yasuda ,  Yasuo Hirata ,  Shuji Murakami ,  Katsuhiro Nakamura ,  Yukitsuna Furuya

IPC分类号： H03M13/33 ,  H04L7/00 ,  H04L7/02 ,  H04L7/04

CPC分类号： H03M13/33 ,  H04L7/0062

摘要： A Viterbi decoder synchronization circuit comprises a phase shifter for introducing a variable amount of delay time to a received bit stream of convolutional codes in response to a control signal applied thereto with respect to a word synchronization signal which is derived from the bit stream. A first detector detects maximum and minimum metric values of the Viterbi decoder. A second detector detects the difference between the detected maximum and minimum metric values for coupling to an integrator. The output of the integrator is applied to a third detector which detects when the integrator output reaches a value indicative of a word-in-sync or word-out-of-sync condition. A phase shift signal is generated in response to an output signal from the third detector and applied to the phase shifter as the control signal.

摘要翻译： 维特比解码器同步电路包括一个移相器，用于响应于从比特流导出的字同步信号施加的控制信号，将可变量的延迟时间引入到所接收的卷积码比特流中。 第一检测器检测维特比解码器的最大和最小度量值。 第二检测器检测检测到的与积分器耦合的最大和最小度量值之间的差异。 积分器的输出被施加到第三检测器，该第三检测器检测积分器输出何时达到指示同步字或字不同步条件的值。 响应于来自第三检测器的输出信号产生相移信号，并将其作为控制信号施加到移相器。

公开(公告)号：US4527279A

公开(公告)日：1985-07-02

申请号：US511774

申请日：1983-07-06

申请人： Yutaka Yasuda ,  Yasuo Hirata ,  Shuji Murakami ,  Katsuhiro Nakamura ,  Yukitsuna Furuya

发明人： Yutaka Yasuda ,  Yasuo Hirata ,  Shuji Murakami ,  Katsuhiro Nakamura ,  Yukitsuna Furuya

IPC分类号： H03M13/33 ,  H04L7/04

CPC分类号： H03M13/33

摘要： A Viterbi decoder synchronization circuit comprises a circuit that derives a word synchronization signal from a received bit stream of convolutional codes. A first detector detects a maximum of metric values derived from the Viterbi decoder at different locations in time. A memory is provided for storing therein the address codes derived at different times and the maximum metric values detected by the first detector. A second detector is connected to the memory for detecting the presence of a path between the states addressed by the address codes stored in the memory. An integrator is connected to the second detector to integrate its output signal. To the integrator is connected a third detector which detects when the integrator output reaches a value indicative of one of word-in-sync and word-out-of-sync conditions of the Viterbi decoder. A phase shift signal is generated in response to an output signal from the third detector and applied to a phase shifter to introduce a delay time to the bit stream.

摘要翻译： 维特比解码器同步电路包括从接收到的卷积码的比特流导出字同步信号的电路。 第一检测器在不同的时间点检测从维特比解码器导出的度量值的最大值。 提供存储器，用于在其中存储在不同时间导出的地址码和由第一检测器检测的最大度量值。 第二检测器连接到存储器，用于检测由存储在存储器中的地址码寻址的状态之间的路径的存在。 积分器连接到第二检测器以整合其输出信号。 连接到积分器的第三检测器，其检测积分器输出何时达到表示维特比解码器的同步字和同步字的其中一个的值。 响应于来自第三检测器的输出信号产生相移信号，并将其应用于移相器以向该比特流引入延迟时间。

公开(公告)号：US08335153B2

公开(公告)日：2012-12-18

申请号：US12913266

申请日：2010-10-27

申请人： Masaki Ichihara ,  Yukitsuna Furuya

发明人： Masaki Ichihara ,  Yukitsuna Furuya

IPC分类号： H04J11/00

CPC分类号： H04L5/0046 ,  H04L5/0007 ,  H04L5/006 ,  H04L5/0064 ,  H04L5/06 ,  H04L27/183 ,  H04L27/2604 ,  H04L27/3488

摘要： To provide an orthogonal frequency division multiplex modem circuit which can multiplex signals, whose bit rates and QoS are different from one another, and can transmit the signals via one OFDM line. A serial/parallel converter converts input signals into a complex parallel signal respectively, and a sub carrier and a modulation system are assigned every communication channel. A randomizer changes the alignment sequence of the signal, a discrete inverse Fourier transformer processes the signal, a parallel/serial converter converts the signal into a serial signal, and a transmitter performs the orthogonal modulation of the signal to output the signal from an antenna. A receiver performs orthogonal demodulation of the signal received with an antenna, a serial/parallel converter converts the signal into a parallel signal, and a discrete Fourier transformer processes the parallel signal. In addition, a de-randomizer restores the alignment sequence of the subcarriers into the original condition, and a parallel/serial converter decodes and outputs the signal.

摘要翻译： 提供一种正交频分复用调制解调器电路，其可以将其比特率和QoS彼此不同的信号进行复用，并且可以经由一条OFDM线路发送信号。 串行/并行转换器将输入信号分别转换成复并行信号，每个通信信道分配一个子载波和一个调制系统。 随机化器改变信号的对准顺序，离散傅里叶逆变换器处理信号，并行/串行转换器将信号转换成串行信号，并且发射机执行信号的正交调制以从天线输出信号。 接收机对由天线接收的信号执行正交解调，串/并转换器将信号转换为并行信号，离散付里叶变换器处理并行信号。 此外，去随机器将子载波的对准序列恢复到原始状态，并行/串行转换器解码并输出信号。

公开(公告)号：US20080008229A1

公开(公告)日：2008-01-10

申请号：US11766303

申请日：2007-06-21

申请人： Kojiro Hamabe ,  Yukitsuna Furuya

发明人： Kojiro Hamabe ,  Yukitsuna Furuya

IPC分类号： H04B7/26

CPC分类号： H04B7/2621 ,  H04W72/082

摘要： A cellular system according to an exemplary aspect of the present invention is a cellular system in which a plurality of frequency carriers are available for communication between a base station and a mobile station, including: a first measurement unit for measuring a rate of time that interference power of a frequency carrier in uplink is more than a pre-determined threshold; a carrier availability/unavailability determining unit for putting the frequency carrier into an unavailable state if the time rate is more than a first threshold and putting the frequency carrier into an available state if the time rate is less than a second threshold; and a communication unit for using the frequency carrier in an available state for the communication between the base station and the mobile station.

摘要翻译： 根据本发明的示例性方面的蜂窝系统是其中多个频率载波可用于基站和移动站之间的通信的蜂窝系统，包括：第一测量单元，用于测量所述干扰的时间速率 上行链路中频率载波的功率大于预定阈值; 载波可用性/不可用性确定单元，用于如果所述时间速率大于第一阈值，则将所述频率载波置于不可用状态，并且如果所述时间速率小于第二阈值，则将所述频率载波置于可用状态; 以及通信单元，用于在可用状态下使用该频率载波进行基站与移动台之间的通信。

公开(公告)号：US07099268B2

公开(公告)日：2006-08-29

申请号：US09879323

申请日：2001-06-12

申请人： Masaki Ichihara ,  Yukitsuna Furuya

发明人： Masaki Ichihara ,  Yukitsuna Furuya

IPC分类号： H04J11/00

CPC分类号： H04L5/0046 ,  H04L5/0007 ,  H04L5/006 ,  H04L5/0064 ,  H04L5/06 ,  H04L27/183 ,  H04L27/2604 ,  H04L27/3488

摘要： To provide an orthogonal frequency division multiplex modem circuit which can multiplex signals, whose bit rates and QoS are different from one another, and can transmit the signals via one OFDM line. A serial/parallel converter converts input signals into a complex parallel signal respectively, and a sub carrier and a modulation system are assigned every communication channel. A randomizer changes the alignment sequence of the signal, a discrete inverse Fourier transformer processes the signal, a parallel/serial converter converts the signal into a serial signal, and a transmitter performs the orthogonal modulation of the signal to output the signal from an antenna. A receiver performs orthogonal demodulation of the signal received with an antenna, a serial/parallel converter converts the signal into a parallel signal, and a discrete Fourier transformer processes the parallel signal. In addition, a de-randomizer restores the alignment sequence of the subcarriers into the original condition, and a parallel/serial converter decodes and outputs the signal.

摘要翻译： 提供一种正交频分复用调制解调器电路，其可以将其比特率和QoS彼此不同的信号进行复用，并且可以经由一条OFDM线路发送信号。 串行/并行转换器将输入信号分别转换成复并行信号，每个通信信道分配一个子载波和一个调制系统。 随机化器改变信号的对准顺序，离散傅里叶逆变换器处理信号，并行/串行转换器将信号转换成串行信号，并且发射机执行信号的正交调制以从天线输出信号。 接收机对由天线接收的信号执行正交解调，串/并转换器将信号转换为并行信号，离散付里叶变换器处理并行信号。 此外，去随机器将子载波的对准序列恢复到原始状态，并行/串行转换器解码并输出信号。

公开(公告)号：US5748668A

公开(公告)日：1998-05-05

申请号：US798874

申请日：1997-02-11

申请人： Hideho Tomita ,  Masahiro Ooki ,  Yukitsuna Furuya

发明人： Hideho Tomita ,  Masahiro Ooki ,  Yukitsuna Furuya

IPC分类号： H04B1/707 ,  H04B7/26 ,  H04W84/12 ,  H04W88/02 ,  H04K1/00

CPC分类号： H04B1/707 ,  H04B7/2625

摘要： In a spread spectrum device including a serial to parallel converter (14) for converting a serial information signal (10) into a parallel signal of n bits, where n represents an integer not smaller than two, an information modulator (20) carries out information modulation on m bits among the n bits of the parallel signal and produces a modulated information signal, where m represents a positive integer smaller than n. A selective spreading code producing circuit (21, 22) has spectrum spreading codes which are equal in number to 2.sup.(n-m) and are different from one another. The selective spreading code producing circuit selectively produces, as a selected spreading code, one of the spectrum spreading codes that is specified by remaining (n-m) bits among the n bits of the parallel signal. A spectrum spreading circuit (23) carries out spectrum spreading on the modulated information signal on the basis of the selected spreading code and produces a spectrum spread signal (13). The spectrum spread signal may be transmitted by a radio portion (18) as a radio information signal (11).

摘要翻译： 在包括用于将串行信息信号（10）转换为n位并行信号的串行到并行转换器（14）的扩展频谱装置中，其中n表示不小于2的整数，信息调制器（20）执行信息 对并行信号的n位中的m位进行调制，并产生调制信息信号，其中m表示小于n的正整数。 选择性扩展码产生电路（21,22）具有数量相等于2（n-m）且彼此不同的频谱扩展码。 选择性扩展码产生电路选择性地产生由并行信号的n位中的剩余（n-m）位指定的频谱扩展码之一作为所选择的扩展码。 频谱扩展电路（23）根据所选择的扩展码对调制信息信号进行频谱扩展，并产生频谱扩展信号（13）。 频谱扩展信号可以由无线电部分（18）作为无线信息信号（11）发送。

公开(公告)号：US5625639A

公开(公告)日：1997-04-29

申请号：US325701

申请日：1994-10-19

申请人： Hideho Tomita ,  Masahiro Ooki ,  Yukitsuna Furuya

发明人： Hideho Tomita ,  Masahiro Ooki ,  Yukitsuna Furuya

IPC分类号： H04B1/707 ,  H04B7/26 ,  H04W84/12 ,  H04W88/02 ,  H04H1/00

CPC分类号： H04B1/707 ,  H04B7/2625

摘要： In a spread spectrum device including a serial to parallel converter (14) for converting a serial information signal (10) into a parallel signal of n bits, where n represents an integer not smaller than two, an information modulator (20) carries out information modulation on m bits among the n bits of the parallel signal and produces a modulated information signal, where m represents a positive integer smaller than n. A selective spreading code producing circuit (21, 22) has spectrum spreading codes which are equal in number to 2.sup.(n-m) and are different from one another. The selective spreading code producing circuit selectively produces, as a selected spreading code, one of the spectrum spreading codes that is specified by remaining (n-m) bits among the n bits of the parallel signal. A spectrum spreading circuit (23) carries out spectrum spreading on the modulated information signal on the basis of the selected spreading code and produces a spectrum spread signal (13). The spectrum spread signal may be transmitted by a radio portion (18) as a radio information signal (11).

摘要翻译： 在包括用于将串行信息信号（10）转换为n位并行信号的串行到并行转换器（14）的扩展频谱装置中，其中n表示不小于2的整数，信息调制器（20）执行信息 对并行信号的n位中的m位进行调制，并产生调制信息信号，其中m表示小于n的正整数。 选择性扩展码产生电路（21,22）具有数量相等于2（n-m）且彼此不同的频谱扩展码。 选择性扩展码产生电路选择性地产生由并行信号的n位中的剩余（n-m）位指定的频谱扩展码之一作为所选择的扩展码。 频谱扩展电路（23）根据所选择的扩展码对调制信息信号进行频谱扩展，并产生频谱扩展信号（13）。 频谱扩展信号可以由无线电部分（18）作为无线信息信号（11）发送。

公开(公告)号：US20060209673A1

公开(公告)日：2006-09-21

申请号：US11441257

申请日：2006-05-25

申请人： Masaki Ichihara ,  Yukitsuna Furuya

发明人： Masaki Ichihara ,  Yukitsuna Furuya

IPC分类号： H04J11/00

CPC分类号： H04L5/0046 ,  H04L5/0007 ,  H04L5/006 ,  H04L5/0064 ,  H04L5/06 ,  H04L27/183 ,  H04L27/2604 ,  H04L27/3488

摘要： To provide an orthogonal frequency division multiplex modem circuit which can multiplex signals, whose bit rates and QoS are different from one another, and can transmit the signals via one OFDM line. A serial/parallel converter converts input signals into a complex parallel signal respectively, and a sub carrier and a modulation system are assigned every communication channel. A randomizer changes the alignment sequence of the signal, a discrete inverse Fourier transformer processes the signal, a parallel/serial converter converts the signal into a serial signal, and a transmitter performs the orthogonal modulation of the signal to output the signal from an antenna. A receiver performs orthogonal demodulation of the signal received with an antenna, a serial/parallel converter converts the signal into a parallel signal, and a discrete Fourier transformer processes the parallel signal. In addition, a de-randomizer restores the alignment sequence of the subcarriers into the original condition, and a parallel/serial converter decodes and outputs the signal.

公开(公告)号：US20050050430A1

公开(公告)日：2005-03-03

申请号：US10924216

申请日：2004-08-24

申请人： Yukitsuna Furuya

发明人： Yukitsuna Furuya

IPC分类号： H04N7/14 ,  H04B1/707 ,  H04J13/00 ,  H04L1/00 ,  H04N19/00 ,  H04N19/33 ,  H04N19/65 ,  H04N19/70 ,  H04N19/89 ,  H04N19/96 ,  H04N21/438 ,  H03M13/00 ,  G01R31/28

CPC分类号： H04N7/17309 ,  H04N19/187 ,  H04N19/37 ,  H04N19/60 ,  H04N19/61 ,  H04N21/234327 ,  H04N21/2383 ,  H04N21/41407 ,  H04N21/4382 ,  H04N21/6131

摘要： A system is provided for efficiently utilizing a transmission capacity without complicated processing by using a hierarchical code comprised of a plurality of layers having different error correcting capabilities. In a transmitter, an encoding unit encodes an image in accordance with a hierarchical coding scheme to generate a plurality of layer data. An error correcting code addition unit performs error correction coding on each of at least one layer data including the lowermost layer data in accordance with an error correction coding scheme which gives higher error correcting capabilities to a lower layer than a higher layer. A transmission unit transmits each of the layer data and error correcting codes onto a transmission path. A receiver corrects possible errors introduced on the transmission path into the layer data received from the transmitter in accordance with the error correction coding scheme, and decodes layer data received in a quality available for decoding to restore the image.

摘要翻译： 提供了一种系统，用于通过使用由具有不同纠错能力的多个层组成的分层代码来有效利用传输容量而不需要复杂的处理。 在发射机中，编码单元根据分层编码方案对图像进行编码，以生成多个层数据。 纠错码相加单元根据向较低层提供较高纠错能力的纠错编码方案对包括最底层数据的至少一层数据进行纠错编码。 发送单元将每个层数据和纠错码发送到传输路径上。 接收机根据纠错编码方案将在传输路径上引入的可能的错误校正到从发射机接收的层数据中，并且以可用于解码的质量接收的层数据解码以恢复图像。

公开(公告)号：US06363100B1

公开(公告)日：2002-03-26

申请号：US08363315

申请日：1994-12-23

申请人： Masahiro Ohki ,  Yukitsuna Furuya

发明人： Masahiro Ohki ,  Yukitsuna Furuya

IPC分类号： H04K100

CPC分类号： H04L27/2082 ,  H04L27/22

摘要： In a transmission side, a k-bit parallel signal is divided into n signals, which are respectively encoded and then phase-shifted so as to causing a mutual phase difference of &pgr;/2n. Spectrum spreading is performed on the phase-shifted encoded signals which are combined together to produce a transmission digital signal. In a receiving side, reverse spreading is performed on a receiving signal to produce reverse-spread signals, which are given the phase difference to cancel the phase shift of the transmission side, and then decoded. Thus, the original k-bit parallel signal is reproduced in the receiving side.

摘要翻译： 在发送侧，将k比特并行信号分割为n个信号，分别对其进行编码，然后进行相移，使π/ 2n的相位差相互相差。 对组合在一起的相移编码信号执行频谱扩展以产生传输数字信号。 在接收侧，对接收信号进行反向扩展，产生反向扩展信号，给予相位差以消除发送侧的相移，然后进行解码。 因此，在接收侧再现原来的k位并行信号。