A decoder circuit used in a semiconductor memory device including a first and second voltage terminals; a NOR gate circuit including a plurality of inverter transistors for receiving address signals and connected in parallel between the first voltage terminal and a common output node, and a positive feedback transistor for positively feeding back a signal on the common output node and operatively connected between the second voltage terminal and the common output node; and a device, operatively connected between the second voltage terminal and the common output node, for conductively connecting the second voltage terminal to the node for a predetermined period in response to the changing of the address signals.